JEDEC is the global leader in developing open standards for the microelectronics industry, with more than 3,000 volunteers representing nearly 300 member companies.
JEDEC brings manufacturers and suppliers together to participate in more than 50 committees and subcommittees, with the mission to create standards to meet the diverse technical and developmental needs of the industry.
JEDEC’s collaborative efforts ensure product interoperability, benefiting the industry and ultimately consumers by decreasing time-to-market and reducing product development costs.
JEDEC publications and standards are accepted throughout the world, and are free and open to all.
JEDEC is accredited by ANSI and maintains liaisons with numerous standards bodies throughout the world.
JEDEC has published JEP194: Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs, JEP195: Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion and JEP192: Guidelines for Gate Charge (QG) Test Method for SiC MOSFET, all of which cover several very important topics pertaining to reliability and testing of SiC MOSFETs. The publications were developed by JEDEC's JC-70.2 Silicon Carbide Subcommittee and are available for free download from the JEDEC website.
Competing standards complicate advances in V2V tech
The battle is on to see which standard -- dedicated short-range communications (DSRC) or Qualcomm's cellular vehicle-to-everything (C-V2X) -- will emerge dominant in vehicle-to-vehicle communication, which researchers say could prevent hundreds of thousands of collisions each year. John Koon sorts out the competitors in this article, pointing out that "[b]oth camps have support from OEMs and technology companies globally."
Full Story: Semiconductor Engineering
JEDEC publishes update to Universal Flash Storage (UFS) standard
JEDEC JESD220F: Universal Flash Storage 4.0 and two complementary standards are available for download from the JEDEC website.
The complementary standards are JESD223E UFSHCI 4.0 standard, and a new companion standard for UFS version 3.1 and above, JESD231 File Based Optimization. Developed for mobile applications and computing systems requiring high performance with low power consumption,
UFS 4.0 introduces significant bandwidth and data protection improvements over the earlier version of the standard.
JEDEC's JC-14.7 Subcommittee announces updated scope
The JC-14.7 Radio Frequency Reliability and Quality Standards subcommittee has modified its scope to respond to industry needs for standardization and needs related to radio frequency devices. The subcommittee is responsible for developing and establishing industry guidelines and standards for discrete devices and integrated circuits (including monolithic microwave integrated circuits, MMICs), that employ semiconductor technologies used in radio frequency (RF), microwave and millimeter wave (mmW) amplification and signal conditioning applications such as radar, satellite communications and 5G and beyond. The focus is on reliability verification and qualification procedures, DC and RF stress/test methods and measurement techniques as well as unique packaging reliability aspects. Upcoming JC-14.7 meetings are May 9th in Monterey, Calif., directly after the ROCS Workshop, and September 22nd in Denver, Colo. To learn more about participation and JEDEC membership, and to register for the Reliability of Compound Semiconductors (ROCS) Workshop on May 9th, visit www.jedec.org.
Qualcomm ceases selling products to Russian companies
Qualcomm says it is no longer selling microchips and other products to companies in Russia. "We comply with US sanctions & laws, are not selling products to Russian companies," says Nate Tibbits, Qualcomm's senior vice president of government affairs.
Full Story: Times of San Diego/Reuters (3/16)
SiFive raises $175M in new funding at a $2.5B valuation
SiFive, the chip design firm using the open-source RISC-V instruction-set architecture, has raised $175 million in a new private funding round, valuing the company at $2.5 billion. Coatue Management led the round and was joined by Intel Capital, Qualcomm Ventures, SK Hynix, Western Digital Capital and other investors.
Full Story: VentureBeat (3/16)
Intel and Micron CEOs will testify at US Senate hearing
The CEOs of Intel and Micron Technology will testify next week at a hearing of the US Senate Commerce Committee, urging lawmakers to provide $52 billion in federal funding for semiconductor manufacturing in the US. The CEO of Paccar, a truck maker, also is scheduled to testify at the committee hearing to talk about the current vulnerabilities in semiconductor supply chains.
Full Story: Reuters (3/16)
Electronics Weekly (UK) (3/17)
Yonhap News Agency (South Korea) (3/17)
DigiTimes (3/17)
Analysis: EVs need integrated GaN components
Fully integrated gallium nitride circuits can be as useful as silicon-based ICs, especially for electric vehicles, Katherine Derbyshire writes. "The transition from individual GaN devices to integrated GaN circuits, and from laboratory proofs of concept to commercial applications, inevitably bring reliability and operating envelope questions to the forefront," Dergyshire concludes.
Full Story: Semiconductor Engineering (3/17)
DDR5 Workshop, Memory Tutorial and Server/Cloud Computing/Edge Forum — Register today!
Join us for the JEDEC DDR5 Workshop, Memory Tutorial and Server/Cloud Computing/Edge Forum in Santa Clara, CA May 23-26, 2022. Single-event a la carte registration is now open, but space is filing quickly so be sure to save your seat soon!
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Semiconductors in Action
Chip vendors order Silicon Motion's PCIe SSD controllers
Silicon Motion Technology is getting orders from leading microchip vendors for the company's PCIe Gen4 SSD controller chips. Silicon Motion expects to take market share of 50% in the PC OEM market segment during the coming months.
Full Story: DigiTimes (3/17)
Fraunhofer IPMS debuts RISC-V IP core for AI at the edge
The Fraunhofer Institute for Photonic Microsystems is offering the EMSA5 processor core, based on the open-source RISC-V instruction-set architecture. The core can be used in designing microchips for artificial intelligence applications at the network edge.
Full Story: New Electronics (3/17)
Innovation: Beyond the Buzzword
Hype surrounding innovation often obscures the focused, multifaceted efforts that make breakthroughs possible. Our research uncovers what drives the successful corporate innovation programs that are recreating the enterprise. Read the study.
Testing & Standards
Chiplet-based exascale supercomputers become a reality
Multiple organizations are developing supercomputing systems based on chiplet technology, Mark LaPedus writes. Hyperion Research forecasts the supercomputer market will increase from $6.6 billion last year to $7.8 billion this year.
Full Story: Semiconductor Engineering (3/17)
JEDEC News
- JEP187: Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets
- JEP186: Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices
- JESD22-A120C: Test Method for the Measurement of Moisture Diffusivity and Water Solubility in Organic Materials Used in Electronic Devices
- JESD78F: IC Latch-Up Test
- JEP151A: Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices
JESD82-521: DDR5 Buffer Definition (DDR5DB01)
JESD305: DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Specification
JESD238: High Bandwidth Memory DRAM (HBM3)
JESD302-1: TS5111, TS5110 Serial Bus Thermal Sensor Device Standard
JESD315: Backup Energy Module Standard for NVDIMM Memory Devices (BEM)
ESD403-1A: JEDEC Module Sideband Bus (SidebandBus)
JEDEC announces the publication of the following new or updated documents:
JESD216E, Serial Flash Discoverable Parameters (SFDP)
JESD230E, NAND Flash Interface Interoperability
JESD89-3B, Test Method for Beam Accelerated Soft Error Rate
JESD89-2B, Test Method for Alpha Source Accelerated Soft Error Rate
JESD89-1B, Test Method for Real-Time Soft Error Rate
JEP185, Copy-Exact Process for Manufacturing
JESD31F, General Requirements for Distributors of Commercial and Military Semiconductor Devices
JESD251B, Expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices
JEDEC announces the publication of the following new or updated documents:
JESD230E, NAND Flash Interface Interoperability
JESD89-3B, Test Method for Beam Accelerated Soft Error Rate
JESD89-2B, Test Method for Alpha Source Accelerated Soft Error Rate
JESD89-1B, Test Method for Real-Time Soft Error Rate
JEP185, Copy-Exact Process for Manufacturing
JESD31F, General Requirements for Distributors of Commercial and Military Semiconductor Devices
JESD251B, Expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices
JESD216E, Serial Flash Discoverable Parameters (SFDP)
JEDEC Publishes XFM Embedded and Removable Memory Device Standard
JESD233: XFM Embedded and Removable Memory Device (XFMD) standard is a new universal data storage media providing an NVMe® over PCI Express® interface in a small, thin form factor. The device is designed to bring replaceable storage to devices typically soldered down in IoT devices and embedded applications. Developed by JEDEC's JC-64.1 Subcommittee for Electrical Specifications and Command Protocols, JESD233 is available for download from the JEDEC website.
JEDEC announces the publication of the following new or updated documents:
JESD230E, NAND Flash Interface Interoperability
JESD89-3B, Test Method for Beam Accelerated Soft Error Rate
JESD89-2B, Test Method for Alpha Source Accelerated Soft Error Rate
JESD89-1B, Test Method for Real-Time Soft Error Rate
JEP185, Copy-Exact Process for Manufacturing
JESD31F, General Requirements for Distributors of Commercial and Military Semiconductor Devices
JESD251B, Expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices
JESD49B: Procurement Standard for Known Good Die (KGD)
JESD235D: High Bandwidth Memory (HBM) DRAM - D revision
JESD209-4-1A: ADDENDUM No. 1 to JESD209-4 LPDDR4X
MCP3.12.1: Multichip Packages (MCP)
JESD22-B109C: Flip Chip Tensile Pull
JEP178: ESD Sensitivity Testing - Reporting ESD Withstand Levels on Datasheets
JESD260: Replay Protected Monotonic Counter (RPMC) for Serial Flash Devices
JESD85A: Methods for Calculating Failure Rates in Units of FITs
JEP183 Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs can be used as a common industry guideline for measuring VT of SiC power devices, focused on N-channel vertical structure MOSFET technologies, providing a common baseline for the SiC MOSFET market. For more information and free download, visit the JEDEC website.
JEP183 Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs
JEDEC publishes new DDR4 NVDIMM-P Bus Protocol standard
JESD304-4.01 DDR4 NVDIMM-P Bus Protocol will enable the industry to create advanced memory solutions
JEDEC Selected Standard News
Applicable to PSMA SCDB products
JEP183 Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs can be used as a common industry guideline for measuring VT of SiC power devices, focused on N-channel vertical structure MOSFET technologies, providing a common baseline for the SiC MOSFET market. For more information and free download, visit the JEDEC website.
JEDEC publishes new DDR4 NVDIMM-P Bus Protocol standard
JESD304-4.01 DDR4 NVDIMM-P Bus Protocol will enable the industry to create advanced memory solutions that benefit from the enhanced system performance and novel data availability offered by Persistent Memory devices. JESD304-4.01 DDR4 NVDIMM-P is available for download from the JEDEC website.
JEDEC publishes the following new or updated documents
- JESD79-4-1B: Addendum No. 1 to JESD79-4, 3D Stacked DRAM
- JEP182: Test Method for Continuous-Switching Evaluation of Gallium Nitride Power Conversion Devices
JEDEC publishes the following new or updated documents
- JESD243A: Counterfeit Electronic Parts: Non-Proliferation for Manufacturers
- JESD253: Enclosure Form Factor for SSD Devices, Version 1.0
- JESD79-4-1B: Addendum No. 1 to JESD79-4, 3D Stacked DRAM
- JEP182: Test Method for Continuous-Switching Evaluation of Gallium Nitride Power Conversion Devices
What a year! 2020 created the perfect storm of undersupply and overdemand in the semiconductor industry. What should you be doing now to prepare for the end of the shortage?
Join us May 13th to get a sneak peek into what industry veterans are doing and what they believe are the key factors in surviving the bad times and thriving in the good.
Event agenda includes:
- Keynote Presentation: Short Circuit—The Global Semiconductor Industry and Supply Chain Challenges by leading industry analyst Malcolm Penn of Future Horizons
- Lively roundtable discussion on global challenges facing the industry
- Vistex demo featuring a full spectrum of capabilities
Also, don’t miss your chance to “Ask the Analyst.” We have a limited number of 1:1 sessions with Malcolm Penn. Register now to get your burning industry questions answered!
JEP95 is a compilation of over 3000 pages of outline drawings for microelectronic packages. An annual updating service and complete hard copies are available for purchase in addition to the downloads available on the JEDEC website. Recent updates include Microelectronic Outlines (MO), Microelectronic Standards (MS) and Socket Outlines (SO). Visit the JEP95 webpage for a full list.
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Visit the JEDEC website to download.
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Visit the JEDEC website to download.
JEP95 is a compilation of over 3000 pages of outline drawings for microelectronic packages. An annual updating service and complete hard copies are available for purchase in addition to the downloads available on the JEDEC website. Recent updates include Microelectronic Outlines (MO), Microelectronic Standards (MS) and Socket Outlines (SO). Visit the JEP95 webpage for a full list.
Updated version of JESD22-A104F: Temperature Cycling now available
JESD22-A104F provides a method for determining solid state devices capability to withstand extreme temperature cycling. This standard applies to single-, dual- and triple-chamber temperature cycling and covers component and solder interconnection testing. For more information and download visit the JEDEC website.
Today's Tech Buzz
A primer on the AI chip market
Artificial intelligence chips are very useful in deep learning technology, and technologists have focused on accelerating DL during training and inferencing, Michael Azoff of Kiasco Research writes. "While most of the AI training is performed in the data center (including on hyperscale clouds) and on workstations, the AI inferencing is done everywhere: on the cloud, on the workstation, on the edge," he notes.
Full Story: EE Times (8/6)
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ICs, Memory & More
Under the leadership of CEO Lisa Su, Advanced Micro Devices has become a more competitive company in the semiconductor industry, Asa Fitch and Euirim Choi write. At the same time, Intel has experienced a number of setbacks and is losing market share in data-center chips to AMD, they note.
Full Story: The Wall Street Journal (tiered subscription model) (8/6)
Taiwan chip firms are under attack by Chinese hackers
Wired (tiered subscription model) (8/6)
Foxconn posts July revenue of $13.67B, up 12% from June
DigiTimes (8/7)
SMIC reports Q2 revenue of $938M, profit of $138M
DigiTimes (8/7)
Going Green
McKinsey: Climate change and the supply chain
While acute weather events and the worldwide COVID-19 pandemic are presenting challenges to the global supply chain, more attention needs to be paid to the durable effects posed by climate change, this McKinsey Global Institute analysis notes. "As climate change makes extreme weather more frequent and/or severe, it increases the annual probability of events that are more intense than manufacturing assets are constructed to withstand, increasing the likelihood of supply-chain disruptions," it states.
Full Story: McKinsey (8/6)
Semiconductors in Action
5G notebooks set for 2021 by Intel and MediaTek
Intel and MediaTek brought out the T700 5G modem chip, which will go into laptops and notebooks. The companies are working together to help launch those 5G mobile devices in early 2021, according to MediaTek.
Full Story: DigiTimes (8/7), Engadget (8/6)
40% of Android devices have vulnerable Snapdragon chip
More than 40% of Android devices contain a Qualcomm Snapdragon chip that researchers say has more than 400 vulnerabilities, putting them at risk of malicious activity such as denial of service, data theft and spying. Qualcomm has patched the vulnerabilities, though the threat remains until networks and vendors push updates out to users.
Full Story: CNET (8/6), Forbes (8/6)
Testing & Standards
EDA software piracy is targeted by industry group
SEMI gathered Cadence Design Systems, Mentor Graphics and Synopsys to develop the SEMI Server Certification protocol, intended to foil piracy in electronic design automation software. "Software piracy is a growing challenge and threatens to stifle innovation for EDA companies and customers alike," Cadence's Nimish Modi says.
Full Story: Electronics Weekly (UK) (8/6)
JEDEC News
JEDEC publishes update to JESD22-A113I test method
JESD22-A113I, Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing, is now available for download from the JEDEC website. This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation.
LEARN MORE ABOUT JEDEC:
Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us
JEDEC publishes update to JESD22-A113I test method
JESD22-A113I, Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing, is now available for download from the JEDEC website. This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation.
JEDEC publishes update to JESD22-A113I test method
JESD22-A113I, Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing, is now available for download from the JEDEC website. This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation.
JEDEC releases final DDR5 memory specification
The JEDEC Solid State Technology Association on Tuesday brought out the final specification for DDR5 SDRAM technology. The DDR5 spec will enable memory chips with up to 64 gigabits in density, an increase of four times compared with DDR4, among other improvements.
Full Story: AnandTech (7/14)
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Samsung sets 2030 goals for 6G tech
Samsung Electronics is looking ahead to the commercialization of 6G cellular communications, issuing a white paper called "The Next Hyper-Connected Experience for All." Compared with the current 5G technology, 6G will provide a peak data rate of 1,000 gigabits per second when 6G is available a decade from now, according to Samsung.
Full Story: Pulse by Maeil Business Newspaper (South Korea) (7/15)
§ Phison reduces stake in JV, selling shares to Kingston
DigiTimes (7/15)
§ ESD Alliance: Q1 EDA revenue rises 3.5% to $2.7B
New Electronics (7/15)
§ Sources: MediaTek orders more substrates for 5G devices
DigiTimes (7/15)
Make the Gig Economy Work for You
Working from home is now the new normal for many. How can the self-employed continue to thrive in our changing economy? Download the whitepaper "Solopreneurship and Thriving in the Gig Economy" to learn how to get the most from your workplace of one.
EU sets deadline on Substances of Very High Concern
Manufacturers selling products in European Union Member States must report their use of Substances of Very High Concern by Jan. 5, 2021, to the new European Chemicals Agency database. The Substances of Concern in Products database aims at lowering the generation of waste containing hazardous substances, providing information on improving waste treatment and offering examination for the entirety of a product's lifespan.
Full Story: Electronic Design (7/14)
Campaign Planning Templates
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Graphcore debuts GC200 chip, M2000 IPU Machine
Graphcore introduced the GC200 artificial intelligence chip along with the M2000 IPU Machine, an AI computer. The startup's new Intelligence Processing Unit and the IPU Machine could be competitive with Nvidia's AI offerings, Karl Freund of Moor Insights and Strategy writes.
Full Story: TechCrunch (tiered subscription model) (7/15), Forbes (7/15)
Google, Lenovo turn to AMD for processors
Confidential Virtual Machines for the Google Cloud Engine have been developed by Advanced Micro Devices and Google Cloud, using AMD's second-generation EPYC processors. Meanwhile, AMD introduced the 64-core Ryzen Threadripper Pro chip, which Lenovo Group is using in its ThinkStation P620, available in September.
Full Story: Electronics Weekly (UK) (7/15), CNET (7/14)
Safety-critical IC verification challenged by variables
Nine industry experts talk about the challenge of fabrication variables for safety-critical devices in this roundtable interview. Cylynt CEO Ted Miracco says, "The electronic content in an automobile is just going up, year after year; and the software contribution to that electronic content is also going up, year after year, so things like diagnostics for automobiles, these things used to be done where you'd pull into a repair shop and download data if it was available."
Full Story: Semiconductor Engineering (7/15)
JEDEC welcomes new member companies to the Association
JEDEC is the global leader in developing standards for the microelectronics industry, bringing together thousands of member company volunteers over 100 technical committees and task groups to meet the needs of every segment of the industry. JEDEC is pleased to extend a warm welcome to new member companies: API Tech, Datotek International Co, Denso Corporation, FLC Technology Group, Hypower Microelectronics and Innosilicon Technology.
Interested in JEDEC membership for your company? Find out more and join today.
News for and about the microelectronics industry
Today's Tech Buzz
Analog Devices will buy Maxim for $20B+
Analog Devices agreed to acquire Maxim Integrated Products in a stock-swap valued at more than $20 billion; the transaction is expected to close a year from now, pending regulatory approval. Once the acquisition closes, Maxim shareholders will own about 31% of the combined company's shares.
Full Story: The Wall Street Journal (tiered subscription model) (7/12),
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ICs, Memory & More
Qualcomm Ventures invests in Jio Platforms
Qualcomm Ventures is investing about $97 million for an equity stake of 0.15% in Jio Platforms, the mobile telecommunications subsidiary of India's Reliance Industries conglomerate. Meanwhile, Soitec completed an agreement with Qualcomm Technologies for the use of piezoelectric-on-insulator engineered substrates which will be targeted for use for 4G and 5G radio-frequency filters.
Full Story: CNN (7/13), New Electronics (7/13)
§ Samsung Electro-Mechanics improves MLCCs for auto uses
Pulse by Maeil Business Newspaper (South Korea) (7/13)
§ IPnest: Interface IP market to expand to $1.8B by 2025
Electronics Weekly (UK) (7/13)
§ MediaTek posts Q2 revenue of $2.3B, topping guidance
DigiTimes (7/13)
Campaign Planning Templates
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Going Green
How to achieve low-power chip verification using ML
Machine learning technology can be used in analyzing the verification of low-power microchip designs, Himanshu Bhatt and Susantha Wijesekara of Synopsys write. "Machine learning-enabled root cause analysis is enabling both design and verification engineers to boost their verification productivity, ensuring a 'shift-left' in the verification turnaround time," they conclude.
Full Story: Semiconductor Engineering (7/13)
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Semiconductors in Action
Amphenol RF expands high-frequency SMA connector line
Amphenol RF brought out extended-frequency cable-mount connectors supporting up to 34 gigahertz as part of its high-frequency subminiature version A connector product line. The connectors can be used in 5G wireless infrastructure, military electronics, radar systems and radio-frequency identification.
Full Story: Electronics Weekly (UK) (7/13)
Report: Apple will ship Arm-based MacBooks in Q4
Ming-Chi Kuo of TF International Securities says Apple may ship Arm-based MacBook Pro and MacBook Air models with its custom-designed processors during the fourth quarter of this year. The MacBook Air with the A-Series chips may slip into early 2021.
Full Story: CNET (7/10)
Testing & Standards
Analysis: Pumping up value in the post-Moore's Law era
The scaling provided during the five decades of Moore's Law chip designs will be much more difficult in the near future, Brian Bailey writes, making the value proposition more challenging. Dhaval Parikh of Arm says, "As the demand for scalable cloud-native applications grow, hyperscale data center operators can greatly benefit by deploying servers that maximize their revenue per deployed server or reduce operating cost when used to deploy an internal service."
Full Story: Semiconductor Engineering (7/13)
JEDEC News
JEDEC welcomes new member companies to the Association
JEDEC is the global leader in developing standards for the microelectronics industry, bringing together thousands of member company volunteers over 100 technical committees and task groups to meet the needs of every segment of the industry. JEDEC is pleased to extend a warm welcome to new member companies: Shenzhen Spark, Semiconductor Technology Co., Shenzhen Sunlord Electronics Co., SkyeChip, Würth Elektronik eiSos, Xsight Labs and Yeestor Microelectronics Co.
Interested in JEDEC membership for your company? Find out more and join today.
LEARN MORE ABOUT JEDEC:
Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us
News for and about the microelectronics industry
Today's Tech Buzz
GlobalFoundries aims to be the DoD's trusted chipmaker
While the world waits to see if Taiwan Semiconductor Manufacturing Co. proceeds with its building a wafer fabrication facility in Arizona, GlobalFoundries is pointing to its potential to serve as a trusted microchip manufacturer for the military/aerospace ecosystem and terminating plans to put up a fab in Chengdu, China.
Full Story: EE Times (7/8)
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ICs, Memory & More
Nvidia overtakes Intel in market value
Nvidia's stock reached a record of $404 a share in Wednesday's trading on the stock market, valuing the chip design company at more than $248 billion. Intel, for years the biggest chipmaker in the world, now is valued at $246 billion.
Full Story: Reuters (7/8), Bloomberg (tiered subscription model) (7/8)
§ Winbond upgrades high-density NOR flash memories
DigiTimes (7/9)
§ Rohm sets up auto power electronics lab JV in China
Electronics Weekly (UK) (7/8)
Taiwan's tech sector challenged by US-China trade war
Taiwan News (7/8)
Campaign Planning Templates
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Going Green
Ultra-low-power device designs for edge, IoT
Designing ultra-low-power devices for edge and internet of things applications present a new set of challenges, Brian Bailey writes. Anoop Saha of Mentor, a Siemens Business, says, "But for IoT devices that are operated by a battery, that is when people start to get concerned about microjoules and picojoules of energy."
Full Story: Semiconductor Engineering (7/9)
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SHIFTING LIVE EVENTS TO WEBINARS
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Semiconductors in Action
Intel details Thunderbolt 4 certification requirements
Intel provided new minimum standards required for the Thunderbolt 4 certification process. Apple will stick with Thunderbolt 4 for its new Macs while the technology remains at moving data at 40 gigabits per second.
Full Story: ZDNet (7/9), TechCrunch (tiered subscription model) (7/8)
Qualcomm aims Snapdragon 865 Plus at gamers, AI
Qualcomm has designed the upcoming Snapdragon 865 Plus especially for artificial intelligence and gaming use, boosting the original 865's clock speed by 10% and enabling peak speeds of 3.6 Gbps. The upgraded chip will also support Wi-Fi 6E technology on smartphones and will render graphics in less time than the previous version did, but will not have an integrated modem.
Full Story: Ars Technica (7/8), The Verge (7/8)
§ MIT team crafts quantum chip with "artificial atoms"
The Independent (London) (tiered subscription model) (7/8)
Testing & Standards
Mashing up computing, data and memory
The inexorable industry push to bring data faster to CPUs is facing new challenges, this analysis notes. Stephen Woo of Rambus says, "The computation is smaller and simpler, so it makes sense to move the data closer to memory."
Full Story: Semiconductor Engineering (7/9)
JEDEC News
JEDEC welcomes new member companies to the Association
JEDEC is the global leader in developing standards for the microelectronics industry, bringing together thousands of member company volunteers over 100 technical committees and task groups to meet the needs of every segment of the industry. JEDEC is pleased to extend a warm welcome to new member companies: Kowin Memory Technology Co., Novatek Microelectronics Corporation, Nuvoton Technology Corporation, proteanTecs, Puya Semiconductor (Shanghai) Co. and Shanghai Fudan Microelectronics Group Co.
Interested in JEDEC membership for your company? Find out more and join today.
TODAY'S TECH BUZZ
SIA: $35B in May chip sales, up 5.8% on year
Global microchip sales reached $35 billion in May, a 5.8% increase from a year earlier and up 1.5% from April of this year, the Semiconductor Industry Association reports. John Neuffer, the SIA's president and CEO, said in a statement, "The global semiconductor market in May remained largely resistant to the widespread economic disruptions caused by the COVID-19 pandemic, but there is still significant uncertainty for the months ahead."
Full Story: New Electronics (7/7)
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ICS, MEMORY & MORE
SMIC to raise funds with stock sale, struggles to compete
While Semiconductor Manufacturing International Corp. stands to take in $7.5 billion from its new listing on the STAR stock market, the Chinese foundry has yet to demonstrate that it can compete with the likes of Taiwan Semiconductor Manufacturing Co. and Samsung Foundry, this analysis notes. SMIC's profit margins aren't promising, and US restrictions on the export of chipmaking technologies could hamper the foundry's potential growth, analysts note.
Full Story: The Wall Street Journal (tiered subscription model) (7/6)
Samsung Electronics posts Q2 earnings of $6.7B, up on year
Yonhap News Agency (South Korea) (free content) (7/7)
Inspur suffers during US-China trade war
DigiTimes (7/7)
Cambricon's IPO raises $368M for AI chip firm
Reuters (7/6)
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GOING GREEN
Team touts development of a new semiconductor material
Researchers at the Samsung Advanced Institute of Technology collaborated with the Ulsan National Institute of Science and Technology and the University of Cambridge to come up with amorphous boron nitride, a semiconducting material. Samsung says this material may be suitable for manufacturing DRAMs and NAND flash memory devices.
Full Story: Neowin (7/6)
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SEMICONDUCTORS IN ACTION
Toshiba develops tech for solid-state LiDAR chips
Toshiba reports the development of a high-resolution, long-range light-receiving technology that could be used for making solid-state LiDAR chips without mechanical components. The company's high-efficiency silicon photo-multiplier may offer an alternative to microelectromechanical system technology in LiDAR devices for automotive applications and other uses.
Full Story: New Electronics (7/7)
Google offers free fabrication for open-source chips
Google debuted the SkyWater process design kit, offering the cost-free fabrication of open-source IC designs with use of the PDK. SkyWater Technology will manufacture those designs with a 130-nanometer process; production runs are limited to 100 chips.
Full Story: Electronics Weekly (UK) (7/6)
TESTING & STANDARDS
Next-generation chips will be data-dependent
Data will determine the lifecycle of a semiconductor design, this analysis notes. "The semiconductor industry has been very good at collecting data, but that data has not been brought together," says Doug Elder of OptimalPlus, an NI Company.
Full Story: Semiconductor Engineering (7/7)
JEDEC NEWS
JEDEC welcomes new member companies to the Association
JEDEC is the global leader in developing standards for the microelectronics industry, bringing together thousands of member company volunteers over 100 technical committees and task groups to meet the needs of every segment of the industry. JEDEC is pleased to extend a warm welcome to new member companies: API Tech, Datotek International Co, Denso Corporation, FLC Technology Group, Hypower Microelectronics and Innosilicon Technology.
Interested in JEDEC membership for your company? Find out more and join today.
EDITOR'S NOTE
Intel resumes shipments to Inspur, invests in telecom
Intel is once again shipping server processors to Inspur, a Chinese manufacturer of servers that was a big customer last year. Meanwhile, the chipmaker is investing $253.5 million for an equity stake of 0.39% in Jio Platforms, India's largest provider of mobile telecommunications.
Full Story: Tom's Hardware (7/3), CNBC (7/3)
ICS, MEMORY & MORE
TSMC invests in production; Samsung tries to catch up
Samsung Electronics is making a big investment in microchip production capacity as it tries to be more competitive with Taiwan Semiconductor Manufacturing Co., the Nikkei Asian Review reports. For its part, TSMC is issuing $470 million in unsecured notes to continue increasing its production capacity.
Full Story: Taiwan News (7/6), Focus Taiwan (7/4)
Samsung's Q2 profit to dip 4.25%, plans 1,000 new hires
Samsung Electronics this week will release preliminary results for the second quarter, likely showing a 4.5% decrease in profit to $5.25 billion as the conglomerate's smartphone sales slumped while the chip business did well in keeping up with demand from data center customers. The company plans to hire 1,000 engineers and scientists in 2020 to work on 5G, artificial intelligence, chip design and other technologies, while industry sources say the chipmaker will pay 100% performance bonuses to semiconductor division employees.
Full Story: Reuters (7/5), The Korea Herald (Seoul) (7/3), Pulse by Maeil Business Newspaper (South Korea) (7/2)
ITRI transfers FRAM, SOT-MRAM tech to chip companies
DigiTimes (7/6)
Nanya posts June revenue of $180.4M, Q2 tops Q1
DigiTimes (7/6)
SMIC's Shanghai share sale to reap $6.55B
Reuters (7/5)
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GOING GREEN
UN: 2019 global e-waste hit 53.6M metric tons
The volume of electronic waste around the world reached 53.6 million metric tons last year, an increase of 9.2 million metric tons over five years, the United Nations reports. Asia was the largest source of e-waste, followed by the Americas, Europe, Africa and Oceania, according to the UN's global e-waste monitor 2020 report.
Full Story: ZDNet (7/3)
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SEMICONDUCTORS IN ACTION
SK Hynix puts HBM2E memory into volume production
SK Hynix reports commencing volume production of HBM2E memory chips. The HBM2E memories provide data transfer rates of up to 3.6 gigabits per second per pin and data storage capacities of up to 16 gigabytes per stack.
Full Story: AnandTech (7/2)
Swiss lab touts single chip with electronics, photonics
ETH Zurich researchers report their development of stacking electronics and photonics components on one chip, connecting them through vias. "We've now overcome the size difference between photonics and electronics by replacing the photonics with plasmonics," says Juerg Leuthold, ETH professor of Photonics and Communications.
Full Story: Electronics Weekly (UK) (7/6)
TESTING & STANDARDS
Experts discuss chip costs, reliability, security
Six industry experts talk about recent developments in the cost, cybersecurity and reliability for next-generation device designs in this roundtable interview. Real Intent CEO Prakash Narain says, "The more customized chip design, the better for us, which is why Cadence and Synopsys have been doing so well."
Full Story: Semiconductor Engineering (7/5)
JEDEC NEWS
JEDEC publishes update to JESD22-A113I test method
JESD22-A113I, Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing, is now available for download from the JEDEC website. This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation.
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JEDEC publishes update to JESD22-A113I test method
JESD22-A113I, Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing, is now available for download from the JEDEC website. This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation.
Visit the JEDEC website for more information and download
https://www.jedec.org/category/technology-focus-area/jc-10/registered-outlines-jep95
JEDEC publishes several new and updated standards:
- JESD79-4C: DDR4 SDRAM Standard
- JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
- JESD246A: Customer Notification Process for Disasters
- JESD22-A105D: Power and Temperature Cycling
- JESD22-B114B: Mark Legibility
- JEP180: Guideline for Switching Reliability Evaluation
- Procedures for Gallium Nitride Power Conversion Devices
- Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
Visit the JEDEC website for more information and download.
Today's Tech Buzz
Analysis: China works on catching up in chip tech
China is pressing ahead with its national program to boost the domestic semiconductor industry with the development of its own extreme ultraviolet lithography system, the beginning of memory chip production and a foundry capable of fabricating microchips with a 14-nanometer FinFET process, Mark LaPedus writes. VLSI Research President Risto Puhakka says, "China is far from being self-sufficient from any reasonable aspect."
Full Story: Semiconductor Engineering (6/22)
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ICs, Memory & More
DRAM prices start to slide, which could weigh on Samsung
DRAMeXchange reports the spot pricing for 8-gigabit DDR4 DRAM was $2.85 on Friday, a decline of 21.6% from $3.637 on April 3, a situation that could cause concern for Samsung Electronics, the world's largest supplier of DRAMs. Meanwhile, the Korean company denied a media report that it plans to relocate its display manufacturing business in China to Ho Chi Minh City in Vietnam.
Full Story: Pulse by Maeil Business Newspaper (South Korea) (6/22), The Korea Herald (Seoul) (6/19), Reuters (6/19)
Toshiba will reduce Kioxia stake, giving cash to investors
Reuters (6/22)
Report: TSMC will keep growing, despite Huawei sales ban
BusinessKorea magazine online (6/22)
ZTE reiterates it designs chips, but doesn't fabricate them
South China Morning Post (Hong Kong) (6/22)
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Going Green
Nordic debuts chip for low-cost, two-layer PCBs
Nordic Semiconductor brought out the nRF52805 Bluetooth 5.2 system-on-a-chip device, which comes in a wafer-level chip-scale package. The low-power compact component is meant for two-layer printed circuit boards.
Full Story: Electronics Weekly (UK) (6/22)
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Semiconductors in Action
Nvidia's A100 GPU will go into 50 server models
The A100 graphics processing unit for applications in data center is being designed into servers from Cisco Systems, Dell Technologies and dozens of other vendors. The GPU's popularity seems to stem from the accompanying A100 PCIe 4.0 card, designed for use in existing server motherboards.
Full Story: CRN (US) (6/22), VentureBeat (6/22)
Honeywell touts its quantum computer as faster than IBM's
Honeywell claimed its newest quantum computer surpasses the performance of IBM's supercomputer, which makes use of quantum computing technology. "What makes our quantum computers so powerful is having the highest quality qubits, with the lowest error rates," Tony Uttley, Honeywell Quantum Solutions president, said in a statement.
Full Story: TechRepublic (6/19)
Testing & Standards
UVVM tech promises to provide faster FPGA verification
The open-source Universal VHDL Verification Methodology is being touted as the fastest method for the verification of field-programmable gate array designs, this article notes. UVVM was launched in 2015 and now is used by around 20% of VHDL FPGA designers.
Full Story: New Electronics (6/22)
JEDEC News
JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.
Today's Tech Buzz
Siemens will buy UltraSoC, adding SoC design analytics
Siemens agreed to acquire UltraSoC, a UK-based provider of analytics and instrumentation for system-on-a-chip device designs, for an undisclosed sum. UltraSoC CEO Rupert Baines said, "We were actually raising a B round, and when we started talking to Siemens, they saw what a strategic fit we were."
Full Story: New Electronics (6/24), EE Times (6/23)
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ICs, Memory & More
Omdia: Chip vendors eke out 2.1% growth in Q1 revenue
The 10 largest suppliers of semiconductors collectively posted first-quarter revenue of $63.6 billion, a 2.1% increase from the fourth quarter of 2019. "Many of the leading semiconductor suppliers benefitted from strong demand for client PCs, enterprise PCs and servers in the first quarter," Omdia's Ron Ellwanger said.
Full Story: DigiTimes (6/24)
Study: Chip industry needs to spread out its wafer fabs
Electronics360 (6/23)
TSMC wants chemical supplier TSCC to set up in the US
The Taipei Times (Taiwan) (6/24)
National Instruments rebrands as NI, purchases OptimalPlus
EE Times (6/24)
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Going Green
ON Semiconductor debuts BLE chip for mesh networking
ON Semiconductor brought out a Bluetooth Low Energy device in an ultra-low-power RSL10 System-in-Package. The product is aimed at mesh networking for applications such as asset tracking and monitoring, building automation, the industrial internet of things, remote environment monitoring and smart homes.
Full Story: New Electronics (6/24)
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Semiconductors in Action
Mercedes-Benz teams with Nvidia for automated driving
Mercedes-Benz and Nvidia will work together on developing a next-generation in-vehicle computing system for automated driving. The software-defined computing architecture will be available in 2024 models of the luxury automobile line.
Full Story: DigiTimes (6/24), Engadget (6/23)
Toshiba unveils 8 n-channel power MOSFETs
Toshiba is extending its DTMOSVI product line, adding eight super junction n-channel power metal-oxide-semiconductor field-effect transistors as part of its . The MOSFETs are rated for 650 volts and can be used in switched-mode power supplies for back-up power sources, data center infrastructure and power conditioners of photovoltaic generators.
Full Story: Electronics Weekly (UK) (6/24)
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Testing & Standards
Analysis: FPGAs are well-suited for machine learning
Field-programmable gate arrays are proving to be useful for machine learning applications, this analysis notes. Shakeel Peera of Microchip Technology says, "FPGAs are specifically better at doing high-performance, low-power applications due to parallelism."
Full Story: Semiconductor Engineering (6/24)
JEDEC News
JEDEC Updates Universal Flash Storage Standard
JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.
Today's Tech Buzz
Qualcomm's Amon touts 5G tech's potential
Cristiano Amon, president of Qualcomm, talks about what 5G cellular communications technology will mean for a variety of applications in this interview. "It allows everything to be connected -- phones, PCs, and lots of machines," he says.
Full Story: Forbes (6/22)
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ICs, Memory & More
China's chip industry looks to 5G, EV, AIoT uses
Colley Hwang, president of DigiTimes, says China's domestic semiconductor industry will benefit from the implementation of 5G, artificial intelligence/internet of things and electric vehicles. China will play a critical role in the EV market, since six of the 10 leading suppliers of EV batteries are based in China, he notes.
Full Story: DigiTimes (6/23)
Intel sees chips with nanowires and nanoribbons by 2025
AnandTech (6/22)
GF plans Fab 8 expansion with property purchase option
Electronics Weekly (UK) (6/23)
4 firms join Silicon Catalyst incubator program
New Electronics (6/23)
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Going Green
Maxim debuts Arm Cortex-M4F MCU for a variety of uses
Maxim Integrated brought out a low-power microcontroller based on the Arm Cortex-M4F core design. The chip is meant for applications in health care, industrial systems and the internet of things.
Full Story: New Electronics (6/23)
Semiconductors in Action
Japan has the fastest supercomputer in the world
The biannual Top500 survey of the world's supercomputers reveals the fastest system now is Fugaku in Kobe, Japan, built by Fujitsu and Riken. The supercomputing system is built around Fujitsu's 48-core A64FX system-on-a-chip device, designed with Arm cores.
Full Story: The Verge (6/23)
Leti's CoolCube process can withstand 500 degrees C
CEA-Leti reports development of the CoolCube process, fully-depleted silicon-on-insulator complementary metal-oxide-semiconductor technology that can produce chips capable of withstanding 500 degrees C during microchip manufacturing. The process could be used in making p-type MOS logic devices, according to the research organization, which collaborated with Samsung Electronics.
Full Story: Electronics Weekly (UK) (6/22)
Testing & Standards
Analysis: Will PAM-8 follow PAM-4 in physical signaling?
PAM-4 is a key standard in high-speed physical signaling today, yet there is conjecture whether there will be a movement toward a PAM-8 standard, Bryon Moyer writes. Saman Sadr of Rambus says, "PAM-8 is not right now being that actively considered," noting that "the amplitude that we can reliably transmit is about 1V peak-to-peak."
Full Story: Semiconductor Engineering (6/23)
JEDEC News
JEDEC welcomes new member companies to the Association
JEDEC is the global leader in developing standards for the microelectronics industry, bringing together thousands of member company volunteers over 100 technical committees and task groups to meet the needs of every segment of the industry. JEDEC is pleased to extend a warm welcome to new member companies 3D Plus, Cyntec Co., ETRI, Global Mixed-mode Technology Inc., Solid State Storage Technology Corporation and Tachyum, Inc. Interested in JEDEC membership for your company? Find out more and join today.
Today's Tech Buzz
GF, SkyWater cut a deal to make US defense chips
GlobalFoundries and SkyWater Technology agreed to act as foundries supplying critical components to the US military and aerospace industry. Senator Patrick Leahy, D-Vt., said, "This partnership helps strengthen a secure supply chain for our nation's most sensitive technology."
Full Story: New Electronics (6/19), Reuters (6/18)
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ICs, Memory & More
Phison will buy a stake in Sony storage unit
Phison Electronics agreed to acquire a 49% equity stake in Nextorage, a Sony Storage Media Solutions subsidiary. Financial terms weren't revealed.
Full Story: DigiTimes (6/19)
SEMI: May's fab gear billings hit $2.35B, up 13.1% on year
DigiTimes (6/19)
Cambridge spinout to lead EU power module consortium
Electronics Weekly (UK) (6/18)
Sources: GPTC wins orders for TSMC chip packaging plant
DigiTimes (6/19)
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Going Green
Team crafts smart textile with graphene
Researchers at the UK's University of Manchester report their development of a graphene-based smart textile that could be woven into clothing. "The next step for this area of research is to address the need for dynamic thermal management of Earth-orbiting satellites," says Professor Coskun Kocabas, the research team leader.
Full Story: New Atlas (6/19)
Semiconductors in Action
Intel debuts a variety of products for AI applications
Intel brought out the third-generation "Copper Lake" Xeon Scalable processors, the Stratix 10-NX field-programmable gate array with a dedicated artificial intelligence engine, Optane memory devices and NAND flash-based solid-state drives. "We believe most of our customers do begin their journey on AI on Xeon," Intel's Lisa Spelman told reporters.
Full Story: EE Times (6/19), ZDNet (6/18)
Samsung offers chip design platform for fabless firms
The Samsung Advanced Foundry Ecosystem Cloud Design Platform was introduced by Samsung Electronics, providing a way for Korean fabless semiconductor companies to develop their own chips. The platform was created in collaboration with Rescale, a provider of high-performance cloud computing applications.
Full Story: Pulse by Maeil Business Newspaper (South Korea) (6/19)
Testing & Standards
Compute-in-memory accelerators present design issues
Using a compute-in-memory accelerator is not an easy replacement for conventional logic, Katherine Derbyshire writes. "Reduced precision is often suggested as a way to improve the computational efficiency of both conventional and CIM systems," she concludes.
Full Story: Semiconductor Engineering (6/18)
JEDEC News
JEDEC publishes several new and updated standards:
- JESD79-4C: DDR4 SDRAM Standard
- JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
- JESD246A: Customer Notification Process for Disasters
- JESD22-A105D: Power and Temperature Cycling
- JESD22-B114B: Mark Legibility
- JEP180: Guideline for Switching Reliability Evaluation
- Procedures for Gallium Nitride Power Conversion Devices
- Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
Visit the JEDEC website for more information and download.
SK Materials becomes a Korean source for chipmaking gas, resist
SK Materials began volume production of high-purity hydrogen fluoride, a gas used in the etching process of semiconductor manufacturing. The Korean company is also investing in a plant to produce photoresist, lessening the dependence of Korean chipmakers on Japanese suppliers of resist.
Full Story: BusinessKorea magazine online
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ICs, Memory & More
Commerce Dept. clears path to developing 5G standards
Commerce Secretary Wilbur Ross defended the government's move to allow American companies to work with Huawei Technologies on developing international standards for 5G cellular communications and other areas. At the same time, he said the US government still suspects Huawei of carrying out industrial espionage and other activities that threaten national security.
Full Story: Reuters
IC Insights: Auto chips will see CAGR of 9.7% into 2024
Electronics Weekly (UK)
Xiaomi aims at auto ICs with BYD Semiconductor funding
DigiTimes
Intel names former HP Inc. CEO Weisler to board
CRN (US)
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Going Green
Team dopes graphene with sodium for battery uses
Researchers at EPFL used sodium dopants in layers of graphene, providing an alternative material to lithium in battery technology. The resulting graphene matrix is said to provide highly efficient storage of energy.
Full Story: Tech Explorist
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Semiconductors in Action
Qualcomm debuts platform for 5G, AI robotics
Qualcomm Technologies brought out the Qualcomm Robotics RB5 platform, a single-board computer based on the company's Snapdragon 845 system-on-a-chip device design. The RB5 platform replaces the RB3, adding artificial intelligence capabilities to the product, with a development kit now available from Thundercomm.
Full Story: EE Times (6/17), AnandTech (6/17)
Rambus unveils IP for high-speed interfaces
Rambus introduced the 112G XSR/USR PHY intellectual property for designing high-speed interface chips. Taiwan Semiconductor Manufacturing Co. can fabricate such chips with its 7-nanometer process.
Full Story: New Electronics (6/18)
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Testing & Standards
GaN and SiC chips look to boost their reliability
Developers of gallium nitride and silicon carbide power devices seek to improve the reliability of those chips, Mark LaPedus writes. David Haynes of Lam Research says, "The smaller form factor and performance of SiC devices is attractive for electric vehicle and hybrid electric vehicle power train applications."
Full Story: Semiconductor Engineering
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JEDEC News
JEDEC Updates Universal Flash Storage Standard
JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.
WT chairman: No boost for consumer chips in 2nd half | Lite-On Tech ramps up production outside of China | SK acquires 1.47% stake in BYD's chip unit for $21M
June 16, 2020
News for and about the microelectronics industry
Today's Tech Buzz
WT chairman: No boost for consumer chips in 2nd half
Eric Cheng, chairman of WT Microelectronics, says in this interview, "Compared with the past seasonal patterns, there may be no peak season for consumer-use chip products in second-half 2020, as strong demand for commercial notebooks in the first half of the year will undermine seasonal demand in the second half, with order visibility for the fourth quarter still relatively opaque." He does expect demand will hold strong for networking chips.
Full Story: DigiTimes (6/16)
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ICs, Memory & More
Lite-On Tech ramps up production outside of China
Lite-On Technology, a provider of electronics manufacturing services, is allocating more production capacity to plants in Brazil, India, Mexico, Taiwan, Thailand and Vietnam, says CEO Warren Chen. By the end of this year, the company will have 15% to 20% of its production capacity in countries other than China, he notes.
Full Story: DigiTimes (6/16)
§ SK acquires 1.47% stake in BYD's chip unit for $21M
Yonhap News Agency (South Korea) (free content) (6/16)
§ Feds allow US firms to work with Huawei on 5G standards
Reuters (6/15)
§ Samsung chief meets with CEO of semiconductor and other units
Pulse by Maeil Business Newspaper (South Korea) (6/16)
Going Green
Moortec debuts a distributed thermal sensor
Moortec Semiconductor brought out an in-chip distributed thermal sensor design, meant to be fabricated with Taiwan Semiconductor Manufacturing Co.'s 5-nanometer process, to monitor thermal activity on microchips, especially those with multiple CPU cores. Moortec CEO Stephen Crosher says, "We've seen a clear need for tighter thermal control of semiconductor devices."
Full Story: EE Times (6/15)
Semiconductors in Action
EDA firms, Microsoft, TSMC take to the cloud for timing signoff
Synopsys worked with Taiwan Semiconductor Manufacturing Co. to optimize the PrimeTime static timing analysis and StarRC parasitic extraction tools running on the Microsoft Azure cloud-based platform. Cadence Design Systems similarly collaborated with TSMC to reduce semiconductor design signoff schedules through the cloud service.
Full Story: New Electronics (6/16), Electronics Weekly (UK) (6/16)
Microchip unveils Adaptec SmartRAID 3100E RAID adapters
Microchip Technology introduced Adaptec SmartRAID 3100E RAID adapters for use in data storage, edge computing and industrial/manufacturing servers. The new products promise to reduce energy consumption by 40%, the company says.
Full Story: New Electronics (6/15)
Testing & Standards
Experts discuss the ins and outs of design verification
Five industry experts talk about how to make design verification faster and simpler in this roundtable interview. Nasr Ullah of SiFive says, "We have to use the same tools that we've used before to be much more thorough, but we also have to figure out how we can integrate all these open-source methodologies in there."
Full Story: Semiconductor Engineering (6/16)
JEDEC News
JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.
LEARN MORE ABOUT JEDEC:
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Today's Tech Buzz
NXP chooses TSMC's 5nm process for auto SoC
NXP Semiconductors is entrusting its latest automotive system-on-a-chip device design to the 5-nanometer process provided by Taiwan Semiconductor Manufacturing Co., skipping over the foundry's 7nm process. NXP and TSMC plan to sample the SoC with key automotive customers during the fall of next year.
Full Story: EE Times (6/12)
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ICs, Memory & More
A look at the wide-bandgap semiconductor market
Gallium nitride and silicon carbide, wide-bandgap semiconductor materials, are gaining in adoption while plain silicon still dominates microchip manufacturing, this analysis notes. Yole Developpement forecasts SiC devices will represent more than 10% of market revenue by 2025, and GaN devices will provide more than 2% of the market by 2025.
Full Story: EE Times (6/12)
§ IC designer Jim Keller departs Intel for "personal reasons"
The Verge (6/12)
§ Synopsys buys Qualtera, adding big data analytics to design
Electronics Weekly (UK) (6/11)
§ Mitsubishi Electric gains PMIC capacity through Sharp deal
Reuters (6/11)
Going Green
Wearables could get a boost from supercapacitor design
An international research team came up with an environmentally friendly, high-performance, low-cost and stretchable supercapacitor that could serve as the power source for wearable gadgets. "We fabricated a prototype with unchanged performance under the 50% strain after a thousand stretching cycles," Skoltech professor Albert Nasibulin said.
Full Story: New Electronics (6/12)
Semiconductors in Action
COVID-19 testing may turn to Bio-FET chips
Biosensing field-effect-transistor devices could be the answer to providing wider testing for COVID-19 infections, AKHAN Semiconductor CEO Adam Khan writes. "To rapidly develop and proliferate this nanocarbon technology, and meet the global demand for faster, more affordable COVID-19 testing, partnerships must be made with labs and businesses that are already working on these biosensor applications for diagnostic systems targeting of SARS-CoV2," he concludes.
Full Story: Electronic Design (6/11)
Winbond debuts its HyperRAM WLCSP package
Winbond Electronics brought out its HyperRAM products contained in wafer-level chip-scale package. The packaging technology is suitable for embedded electronics.
Full Story: New Electronics (6/12)
Testing & Standards
Analysis: 5nm chips are showing their age
Advanced chip designs fabricated with a 5-nanometer process are presenting new challenges in terms of device aging, Brian Bailey writes. "Semiconductor chips that operate in extreme conditions, such as automotive (150° C) or high elevation (data servers in Mexico City) have the highest risk of reliability and aging-related constraints," says Milind Weling of Intermolecular.
Full Story: Semiconductor Engineering (6/11)
JEDEC News
JEDEC Updates Universal Flash Storage Standard
JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.
LEARN MORE ABOUT JEDEC:
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News for and about the microelectronics industry
Today's Tech Buzz
AMD CEO emphasizes security for US chip supply chains
Lisa Su, the CEO of Advanced Micro Devices, supports the Semiconductor Industry Association's push for more federal funding of American chip technology, while adding, "With that comes a need for secure supply chains." Meanwhile, Jon Peddie Research estimates AMD has shipped more than 500 million CPUs in the past seven years, an achievement only outdone by Intel.
Full Story: ZDNet (6/2), Tom's Hardware (6/2)
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ICs, Memory & More
Sources: TSMC adds SAMT as a materials supplier
Solar Applied Materials Technology is providing sputtering target materials to Taiwan Semiconductor Manufacturing Co. for front-end thin-film processes, industry sources say. SEMI notes that sputtering target materials represent around 3% of all materials used in semiconductor production.
Full Story: DigiTimes (6/3)
§ SIA reports April chip sales of $34.4B, rising 6.2% on year
Electronics Weekly (UK) (6/3)
§ Sources: USB chips are in shortage with stay-at-home economy
DigiTimes (6/3)
§ Merck debuts unit for chemicals, materials, semiconductors
The Korea Herald (Seoul) (6/3)
Going Green
ST has nearly eliminated PFOA from its processes
STMicroelectronics reports it has eliminated 94.4% of perfluorooctanoic acid (PFOA) and PFOA-related substances from its semiconductor manufacturing processes on a worldwide basis. The chipmaker has a goal of completely removing PFOA by 2025.
Full Story: Chemical Watch (subscription required) (6/2)
Semiconductors in Action
Imagination intros IEEE 802.11ax/Wi-Fi 6 IP
Imagination Technologies brought out IMG iEW400, intellectual property complying with the IEEE 802.11ax/Wi-Fi 6 standard. The IP can be used for designing chips for hearables, the internet of things and wearables.
Full Story: New Electronics (6/2)
NXP debuts a chip for contactless city services
NXP Semiconductors introduced the MIFARE DESFire EV3 chip meant for use in securely connecting with smart city services. The chip's hardware and software are certified to Common Criteria EAL 5+, the chipmaker reports.
Full Story: New Electronics (6/3)
Testing & Standards
Verifying RISC-V chip designs gets easier
With wider adoption of the open-source RISC-V instruction-set architecture, verifying processor designs are becoming less onerous, this analysis notes. Roddy Urquhart of Codasip says, "Developing and verifying RISC-V designs is not fundamentally different to other processor architectures."
Full Story: Semiconductor Engineering (6/3)
JEDEC News
JEDEC Updates Universal Flash Storage Standard
JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.
LEARN MORE ABOUT JEDEC:
Join JEDEC | Free Standards Download
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JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.
JEDEC publishes several new and updated standards:
- JESD79-4C: DDR4 SDRAM Standard
- JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
- JESD246A: Customer Notification Process for Disasters
- JESD22-A105D: Power and Temperature Cycling
- JESD22-B114B: Mark Legibility
- JEP180: Guideline for Switching Reliability Evaluation
- Procedures for Gallium Nitride Power Conversion Devices
- Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
EDA, verification support crucial to HPC packaging
High-end high performance computing (HPC) chips solutions are entailing ever-rising packaging complexity along with their increasing applications to large-size datacenters and networking equipment beyond handsets, and this has made EDA (electronic design automation) tools and IC verification services growingly crucial to packaging.
The fast spread of the coronavirus pandemic is fueling needs for work-from-home, online teleconferencing and other stay-at-home economic activities, requiring HPCs to handle cloud computing and big data processing via large-size network equipment and datacenters.
Industry sources said with new large-size HPCs requiring ever-higher computing performance, advanced CoWoS packaging process, based on silicon interposer, continues to adopt larger reticles to integrate more SoCs and high bandwidth memory chips. In this regard, EDA tools for the initial simulation support and following reliability analysis and test for HPCs are important in the entire process.
Taiwan-based IC verification specialists such as Integrated Service Technology (iST) and EDA tools providers including Ansys all have roles in the advanced packaging processes. Ansys' newly released RaptorH can help engineers improve design procedures for diverse HPCs such as 5G chips, 3D ICs and RF (radio frequency) ICs for applications to smart mobile devices, antennas, data storage systems and network infrastructure, as well as even autonomous vehicles and industrial control systems, the sources said.
Reliability analysis for large-size network and datacenter HPC solutions adopting advanced packaging technology usually will take two weeks to complete, double that for handset applications and allowing analysts to charge more, the sources continued.
At the moment, foundry giant TSMC's WLSI (wafer level system integration) platform can provide the world's first-tier chipmakers, IDMs and system vendors with sound integrated HPC chips solutions. The company now uses InFo_PoP and InFO-AiP to package iPhone APs and antenna modules, and its derived technologies InFO_oS and InFO_MS will focus on processing networking and datacenter HPCs, the sources said. Dedicated backend houses such as ASE Technology can also use its 2.5D IC packaging technology such as FOCoS to serve chipmakers.
HPC chip packaging complexity calls for EDA, verification
The increasing complexity of advanced packaging for high-performance computing chips is driving demand for electronic design automation software tools and IC verification services. Those HPC chips are going into large-scale data centers and networking equipment.
Full Story: DigiTimes (3/16)
JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.
JEDEC publishes several new and updated standards:
- JESD79-4C: DDR4 SDRAM Standard
- JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
- JESD246A: Customer Notification Process for Disasters
- JESD22-A105D: Power and Temperature Cycling
- JESD22-B114B: Mark Legibility
- JEP180: Guideline for Switching Reliability Evaluation
- Procedures for Gallium Nitride Power Conversion Devices
- Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.
JEDEC Updates Universal Flash Storage Standard
JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.
JEDEC publishes several new and updated standards:
- JESD79-4C: DDR4 SDRAM Standard
- JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
- JESD246A: Customer Notification Process for Disasters
- JESD22-A105D: Power and Temperature Cycling
- JESD22-B114B: Mark Legibility
- JEP180: Guideline for Switching Reliability Evaluation
- Procedures for Gallium Nitride Power Conversion Devices
- Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
JEDEC publishes several new and updated standards:
- JESD79-4C: DDR4 SDRAM Standard
- JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
- JESD246A: Customer Notification Process for Disasters
- JESD22-A105D: Power and Temperature Cycling
- JESD22-B114B: Mark Legibility
- Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
JEP95 is a compilation of some 3000 pages of outline drawings for microelectronic packages. An annual updating service and complete hard copies are available for purchase in addition to the downloads available on the JEDEC website. For more information and recent updates visit the JEP95 page on the JEDEC website.
JEDEC publishes several new and updated standards
- JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
- JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
- JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
- JESD30I: Descriptive Designation System for Electronic-Device Packages
- JESD245C: Byte Addressable Energy Backed Interface
Read more about these standards.
Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us
Today's Tech BuzZ-
Ministry: Japan to make more transistors than the US
Japan's Ministry of International Trade and Industry reports the country will be producing 6 million transistors a month by the end of the year, outdoing the US for monthly transistor manufacturing.
Electronics Weekly (UK) (12/3)
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ICs, Memory & More
Intel's chip shortage drives Dell to look at AMD chips
Dell is considering the use of chips supplied by Advanced Micro Devices in light of Intel's continuing problems in making enough CPUs for market demands. "We are evaluating AMD chips," said Tom Sweet, Dell's chief financial officer, in an interview; adding that the computer manufacturer already uses AMD chips in particular instances.
Yahoo (12/3)
Court upholds Korean fine against Qualcomm; appeal planned
Qualcomm plans to appeal a ruling by a South Korean court upholding an $873 million fine for unfair business practices in patent licensing and modem chip sales. Meanwhile, Qualcomm debuted the 3D Sonic Max ultrasonic in-display fingerprint sensor, which can read two fingerprints at the same time, and revealed some details about the forthcoming Snapdragon 865 Mobile Platform and Snapdragon 765/765G mobile platform.
Reuters (12/3), ZDNet (12/3), The Verge (12/3)
2020 forecasts see single-digit growth for chip sales Electronics Weekly (UK) (12/4)
Going Green
Team touts organic semiconductors for next-gen electronics
Sensors, solar cells and other devices may perform better if made from organic semiconductor materials, Rutgers University researchers report. "If implemented in electrical circuits, such an enhancement - achieved by very slight bending -- would mean a major leap toward realizing next-generation, high-performance organic electronics," said Professor Vitaly Podsorov, senior author of the study.
New Electronics (12/4)
Semiconductors in Action
UNISOC licenses Imagination's AI chip tech
UNISOC licensed the IMG Series3NX neural network accelerator intellectual property from Imagination Technologies for use in designing system-on-a-chip devices for mobile electronics, televisions and other applications. Meanwhile, Imagination brought out the IMG A-Series graphics processing unit IP, representing the 10th generation of its PowerVR GPU architecture.
New Electronics (12/4), Electronics Weekly (UK) (12/3)
Amazon unveils the AWS Graviton 2 processor for data centers Reuters (12/3)
Testing & Standards
Chipmakers consider their options in EUV lithography
Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing Co. are urging ASML to speed up development of its EXE:5000 extreme ultraviolet lithography system with a high-numerical-aperture lens, which could pattern chips with 3-nanometer features. Those chipmakers are currently using the NXE:3340C system for multiple patterning with 5nm/3nm chip production.
Semiconductor Engineering (12/4)
JEDEC News
JEDEC has published document release 5 of the DDR4 Serial Presence Detect (SPD) Specification. With this release of the document, the revision level of all memory types increases to UDIMM (revision 1.2), RDIMM (revision 1.3), LRDIMM (revision 1.4) and NVDIMM (revision 1.2). In addition, JEDEC has issued document release 1 of the DDR4 DIMM Labels Specification.
Learn more about JEDEC:
Join JEDEC | Free Standards Download
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JEDEC News
JEDEC publishes several new and updated standards
- JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
- JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
- JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
- JESD30I: Descriptive Designation System for Electronic-Device Packages
- JESD245C: Byte Addressable Energy Backed Interface
Read more about these standards.
Learn more about JEDEC:
Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us
Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package
Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959
MO-341A
Oct 2019
Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20
MO-340A
Oct 2019
STANDARD MANUFACTURERS IDENTIFICATION CODE
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm
JEP106BA
Oct 2019
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS
JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.
JEP162A
Sep 2019
Registration - Plastic Bottom Flatpack 28 Terminal Package
Item 11-11.975, STP File for MO-339A
MO-339A
Sep 2019
Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package
Item 11.11-973, Access STP Files for MO-338A
MO-338A
Sep 2019
JEDEC News
JEDEC publishes several new and updated standards
- JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
- JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
- JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
- JESD30I: Descriptive Designation System for Electronic-Device Packages
- JESD245C: Byte Addressable Energy Backed Interface
Read more about these standards.
Learn more about JEDEC:
Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us
Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package
Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959 MO-341A Oct 2019 view
Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20 MO-340A Oct 2019 view
STANDARD MANUFACTURERS IDENTIFICATION CODE
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm JEP106BA Oct 2019 view
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS
JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. JEP162A Sep 2019 view
Registration - Plastic Bottom Flatpack 28 Terminal Package
Item 11-11.975, STP File for MO-339A MO-339A Sep 2019 view
Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package
Item 11.11-973, Access STP Files for MO-338A MO-338A Sep 2019 view
JEDEC News
JEDEC publishes several new and updated standards
- JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
- JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
- JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
- JESD30I: Descriptive Designation System for Electronic-Device Packages
- JESD245C: Byte Addressable Energy Backed Interface
Read more about these standards.
Learn more about JEDEC:
Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us
Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package
Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959
MO-341A Oct 2019 view
Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20
MO-340A Oct 2019 view
STANDARD MANUFACTURERS IDENTIFICATION CODE
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm
JEP106BA Oct 2019 view
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS
JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.
JEP162A Sep 2019 view
Registration - Plastic Bottom Flatpack 28 Terminal Package
Item 11-11.975, STP File for MO-339A
MO-339A Sep 2019 view
Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package
Item 11.11-973, Access STP Files for MO-338A
MO-338A Sep 2019 view
JEDEC News
JEDEC publishes several new and updated standards
- JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
- JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
- JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
- JESD30I: Descriptive Designation System for Electronic-Device Packages
- JESD245C: Byte Addressable Energy Backed Interface
Read more about these standards.
Learn more about JEDEC:
Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us
Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package
Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959 MO-341A Oct 2019 view
Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20 MO-340A Oct 2019 view
STANDARD MANUFACTURERS IDENTIFICATION CODE
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm
JEP106BA Oct 2019 view
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS
JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.
JEP162A Sep 2019 view
Registration - Plastic Bottom Flatpack 28 Terminal Package
Item 11-11.975, STP File for MO-339A MO-339A Sep 2019 view
Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package
Item 11.11-973, Access STP Files for MO-338A MO-338A Sep 2019 view
News for and about the microelectronics industry
Today's Tech Buzz
Senators call for stop on Huawei license approvals
Fifteen senators called on the Trump administration to suspend issuing licenses to US companies that do business with Huawei Technologies, claiming the Chinese company presents a threat to national security. In a letter to President Donald Trump, the bipartisan group says the Commerce Department licenses will enable "Huawei to continue to pose a serious threat to US telecommunications infrastructure and national security more broadly."
Reuters (11/21)
ICs, Memory & More
Micron CEO sees "healthy demand trends" in DRAM market
Micron Technology CEO Sanjay Mehrotra credits artificial intelligence, the internet of things and other applications for increasing use of DRAMs. "When I look beyond the calendar first quarter of 2020, I see healthy demand trends for DRAM in all end markets," he said in an interview, adding, "There is still excessive inventory in the DRAM industry and producers, but the inventory is coming down fast."
The Taipei Times (Taiwan) (11/22)
President of S. Korea lauds new silicon wafer plant
President Moon Jae-in attended the opening of MEMC Korea's silicon wafer plant in Cheonan, Korea, saying it would reduce the country's reliance on importing silicon wafers for its semiconductor industry. MEMC Korea is a subsidiary of Taiwan-based GlobalWafers.
The Korea Herald (Seoul)/Yonhap News Agency (11/22)
- Innodisk: IoT devices need remote monitoring and maintenance DigiTimes (11/22)
Going Green
$10M more invested in IoT energy harvesting startup
Disruptive Technology Ventures invested another $10 million in Nowi, a designer of energy harvesting chips, expanding the startup's Series A funding by DTV and the Dutch government. "This new $10 million Series A round of funding enables Nowi to further grow the team and complete the transition from start-up to a mature organization, while still retaining a majority position in the company," said Nowi CEO Simon van der Jagt.
Electronics Weekly (UK) (11/21)
Semiconductors in Action
Supermicro, Intel team for distributed-training AI systems
Super Micro Computer is working with Intel on artificial intelligence systems using the chipmaker's Nervana Neural Network Processor for Training. The processor is a purpose-built, application-specific integrated circuit supporting deep learning training models.
New Electronics (11/21)
Testing & Standards
Panel-level fan-out packaging tech gains in adoption
More companies are turning to panel-level fan-out packaging technology, a successor to wafer-level fan-out packaging, as a method to reduce the costs of advanced packaging, this analysis notes. SEMI is considering a standard on panel sizes, narrowing the specifications to 510mm x 515mm and 600mm x 600mm.
Semiconductor Engineering (11/21)
- Analysis: Wafer bonding is key to 3DIC technology Semiconductor Engineering (11/21)
JEDEC News
JEDEC has published document release 5 of the DDR4 Serial Presence Detect (SPD) Specification. With this release of the document, the revision level of all memory types increases to UDIMM (revision 1.2), RDIMM (revision 1.3), LRDIMM (revision 1.4) and NVDIMM (revision 1.2). In addition, JEDEC has issued document release 1 of the DDR4 DIMM Labels Specification.
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News for and about the microelectronics industry
Today's Tech Buzz
Commerce Dept. to grant, deny licenses for Huawei sales
The US Department of Commerce said Wednesday that it would grant "several licenses" to American companies, allowing them to continue their sales to Huawei Technologies, while adding it would deny some license applications. Broadcom, Google, Intel, Microsoft and Qualcomm all declined to comment on the license issue.
CNN (11/21)
A programmable memristor computer on CMOS
As machine learning and AI demands grow, memory bottlenecks have bogged down innovation. To get around limitations of on-chip memory and the cloud, University of Michigan has made the first memristor-based programmable computer, reports IEEE.
ICs, Memory & More
Intel: PC chip supplies still short, turns to foundries
Intel said its chips for PCs remain in short supply, adding it would provide more orders to foundries for producing those scarce devices. "I'd like to acknowledge and sincerely apologize for the impact recent PC CPU shipment delays are having on your business and to thank you for your continued partnership," Intel's Michelle Johnston Holthaus wrote in a letter to customers and partners.
Reuters (11/20), The Business Journals (tiered subscription model)/Portland, Ore. (11/20)
FOPLP is an alternative to IC scaling, PTI chairman says
Fan-out panel-level packaging technology offers a suitable alternative to continued scaling for chip designs, says DK Tsai, chairman of Powertech Technology. FOPLP can be used to produce high-performance computing chipsets without resorting to advanced process nodes, such as 7-nanometer and 5nm, he asserts.
DigiTimes (11/21)
- Report: 4% of memory wafers in 2020 will run in China Electronics Weekly (UK) (11/21)
Going Green
TT Electronics offers lead-free GBCN for RoHS compliance
TT Electronics expanded its line of GBCN thick-film gate arrays that do not contain lead or lead compounds. These gate arrays are suitable to meet the European Union's Restriction of Hazardous Substances directive, the distributor says.
Electronics Weekly (UK) (11/21)
Semiconductors in Action
Renesas aims at industrial automation with ASSP
Renesas Electronics brought out the ASI4U application-specific standard product chip, complying with the Actuator Sensor Interface version specification version 5 standard. The ASSP is meant for use in industrial networking systems.
New Electronics (11/20)
- Maxim debuts tech for blood pressure monitoring Electronics Weekly (UK) (11/21)
Testing & Standards
DRAM tech approaches its physical limits
DRAM technology is getting closer to its physical limits, making the memory chips harder to produce at 10 nanometers and lower process nodes, Mark LaPedus writes. Gill Lee of Applied Materials wrote in a blog post, "With DRAM, geometric lateral scaling continues, but it is slowing and materials innovation will be needed for further scaling as with 3D NAND."
Semiconductor Engineering (11/21)
JEDEC News
DDR4 design specifications published
Recent updates to JESD21-C: JEDEC Configurations for Solid State Memories include DDR4 Unbuffered DIMM and SODIMM specifications. For more information visit the JESD21-C page on the JEDEC website.
Learn more about JEDEC:
Join JEDEC | Free Standards Download
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SmartBrief offers 200+ newsletters
Learn more about the SmartBrief audience
Contact Us:
Advertising - Brenna Smith
Editor - Susan Rush
Contributing Editor - Jeff Dorsch
Mailing Address:
SmartBrief, Inc.®, 555 11th ST NW, Suite 600, Washington, DC 20004
© 1999-2019 SmartBrief, Inc.®
Privacy Policy (updated May 25, 2018) | Legal Information
October 7-10, 2019 - Santa Clara, CA
October 14-17, 2019 - Hsinchu, Taiwan
LAST CHANCE - Advance Registration Ends 9/27
Join us for exclusive, pre-publication insight into the JEDEC DDR5, LPDDR5 and NVDIMM-P standards. Get ahead of the competition with in-depth technical reviews taught by industry experts involved in the development of these standards.
JEDEC DDR5 memory will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency. These enhancements, combined with a more user-friendly interface for server and client platforms, will enable high performance and improved power management in a wide variety of applications.
The JEDEC NVDIMM-P standard will enable the industry to create Persistent Memory solutions optimized for cost, power utilization and performance. Adding to the existing NVDIMM-N JEDEC standards, NVDIMM-P modules are designed to maximize the benefits of new Persistent Memory media including reduced software overhead, capacity expansion and lowest latency in computing systems.
JEDEC LPDDR5 is designed to significantly boost memory speed and efficiency for a variety of applications including mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. In addition, LPDDR5 offers new features designed for mission critical applications such as automotive.
On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
LAST CHANCE to save: advance registration for Santa Clara ends 9/27! Higher onsite registration rates will go into effect thereafter. Registration is a la carte - pick and choose the topics that interest you.
Registration - CA
Registration - Taiwan
Event Dates & Locations
- October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
- October 7, 2019 - Memory Tutorial Santa Clara, CA
- October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
- October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
- October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
- October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
- October 15-16 - DDR5 Workshop Hsinchu, Taiwan
October 17 - NVDIMM-P Workshop Hsinchu, Taiwan
October 7-10, 2019 - Santa Clara, CA
October 14-17, 2019 - Hsinchu, Taiwan
Register now - registration closes soon!
Join us for exclusive, pre-publication insight into the JEDEC DDR5, LPDDR5 and NVDIMM-P standards. Get ahead of your competition with in-depth technical reviews taught by industry experts involved in the development of these standards.
On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
Act now - space is limited and registration closes 9/27 or when available space is filled!
Registration - CA
Registration - Taiwan
Event Dates & Locations
- October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
- October 7, 2019 - Memory Tutorial Santa Clara, CA
- October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
- October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
- October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
- October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
- October 15-16 - DDR5 Workshop Hsinchu, Taiwan
- October 17 - NVDIMM-P Workshop Hsinchu, Taiwan
Santa Clara Event Sponsor
Industry Sponsor: DDR5 Workshop Santa Clara
Tto download JEDEC standards at www.jedec.org.
Our mailing address is:
JEDEC
3103 North 10th Street
Suite 240S
Arlington, Va 22201
JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Memory Tutorial: A DDR5 Workshop Companion
October 7-10, 2019 - Santa Clara, CA
Register now - online registration ends soon!
The JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops in Santa Clara, CA and Hsinchu, Taiwan will offer participants an unparalleled opportunity to receive an in-depth technical review of these standards. On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
Registration is now open for events in California! Act now - space is limited!
Event Dates & Locations
- October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
- October 7, 2019 - Memory Tutorial Santa Clara, CA
- October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
- October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
- October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
- October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
- October 15-16 - DDR5 Workshop Hsinchu, Taiwan
- October 17 - NVDIMM-P Workshop Hsinchu, Taiwan
Interested in the events in Taiwan? Register here.
Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.
JEDEC Workshops: DDR5, LPDDR5, NVDIMM-P
Memory Tutorial: A DDR5 Workshop Companion
October 7-10, 2019 - Santa Clara, CA
October 14-17, 2019 - Hsinchu, Taiwan
Register now - space is limited
Join us for an in-depth technical review of these standards with industry experts directly involved in their development.
LPDDR5 is designed to significantly boost memory speed and efficiency for a variety of applications including mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. In addition, LPDDR5 offers new features designed for mission critical applications such as automotive.
DDR5 will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency.
NVDIMM-P: As demand for DRAM capacity and bandwidth continues to grow within systems, Hybrid DIMM technologies such as JEDEC NVDIMM-P will enable new memory solutions optimized for cost, power usage and performance.
A companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
Registration is now open for events in California! Act now - space is limited!
Event Dates & Locations
- October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
- October 7, 2019 - Memory Tutorial Santa Clara, CA
- October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
- October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
- October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
- October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
- October 15-16 - DDR5 Workshop Hsinchu, Taiwan
- October 17 - NVDIMM-P Workshop Hsinchu, Taiwan
Interested in the events in Taiwan? Register here.
Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.
Copyright © 2019 JEDEC, All rights reserved.
to download JEDEC standards at www.jedec.org.
Our mailing address is:
JEDEC
3103 North 10th Street
Suite 240S
Arlington, Va 22201
Join us for an in-depth technical review of these standards with industry experts directly involved in their development.
LPDDR5 is designed to significantly boost memory speed and efficiency for a variety of applications including mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. In addition, LPDDR5 offers new features designed for mission critical applications such as automotive.
DDR5 will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency.
NVDIMM-P: As demand for DRAM capacity and bandwidth continues to grow within systems, Hybrid DIMM technologies such as JEDEC NVDIMM-P will enable new memory solutions optimized for cost, power usage and performance.
A companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
Registration is now open for events in California! Act now - space is limited!
Event Dates & Locations
- October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
- October 7, 2019 - Memory Tutorial Santa Clara, CA
- October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
- October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
- October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
- October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
- October 15-16 - DDR5 Workshop Hsinchu, Taiwan
- October 17 - NVDIMM-P Workshop Hsinchu, Taiwan
Interested in the events in Taiwan? Register here
Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.
JEDEC Workshops: DDR5, LPDDR5, NVDIMM-P
Memory Tutorial: A DDR5 Workshop Companion
October 7-10, 2019 - Santa Clara, CA
October 14-17, 2019 - Hsinchu, Taiwan
Register now - space is limited
JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Memory Tutorial: A DDR5 Workshop Companion
October 7-10, 2019 - Santa Clara, CA
Register now - space is limited
The JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops in Santa Clara, CA and Hsinchu, Taiwan will offer participants an unparalleled opportunity to receive an in-depth technical review of these standards. On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
Registration is now open for events in California! Act now - space is limited!
Event Dates & Locations
- October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
- October 7, 2019 - Memory Tutorial Santa Clara, CA
- October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
- October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
- October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
- October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
- October 15-16 - DDR5 Workshop Hsinchu, Taiwan
- October 17 - NVDIMM-P Workshop Hsinchu, Taiwan
Interested in the events in Taiwan? Pre-register here.
Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.
JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Memory Tutorial: A DDR5 Workshop Companion
October 7-10, 2019 - Santa Clara, CA
Register now - space is limited
The JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops in Santa Clara, CA and Hsinchu, Taiwan will offer participants an unparalleled opportunity to receive an in-depth technical review of these standards. On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
Pre-registration is now open for events in California! Act now for discounted pricing on two bundle options. A la carte event registration will be available starting July 17, space permitting.
Event Dates & Locations
- October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
- October 7, 2019 - Memory Tutorial Santa Clara, CA
- October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
- October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
- October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
- October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
- October 15-16 - DDR5 Workshop Hsinchu, Taiwan
- October 17 - NVDIMM-P Workshop Hsinchu, Taiwan
Interested in the events in Taiwan? Pre-register here.
Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.
JEDEC
3103 North 10th Street
Suite 240S
Arlington, Va 22201
-JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Memory Tutorial: A DDR5 Workshop Companion
October 7-10, 2019 - Santa Clara, CA
Register now - space is limited
The JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops in Santa Clara, CA and Hsinchu, Taiwan will offer participants an unparalleled opportunity to receive an in-depth technical review of these standards. On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
Pre-registration is now open for events in California! Act now for discounted pricing on two bundle options. A la carte event registration will be available starting July 17, space permitting. Registration for the events in Taiwan will open soon.
Option #1: Memory Tutorial, DDR5 & NVDIMM-P Workshops
JEDEC Members: $1,050
Non-members: $1,275
Option #2: LPDDR5, DDR5 & NVDIMM-P Workshops
JEDEC Members: $1,275
Non-members: $1,500
Event Dates & Locations
- October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
- October 7, 2019 - Memory Tutorial Santa Clara, CA
- October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
- October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
- October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
- October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
- October 15-16 - DDR5 Workshop Hsinchu, Taiwan
- October 17 - NVDIMM-P Workshop Hsinchu, Taiwan
-Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.