Safety & Compliance Database

Safety & Compliance Info & Resources for
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For copies of Standards, please contact the appropriate agency. PSMA does not provide copies of standards.
JEDEC

JEDEC is the global leader in developing open standards for the microelectronics industry, with more than 3,000 volunteers representing nearly 300 member companies.

JEDEC brings manufacturers and suppliers together to participate in more than 50 committees and subcommittees, with the mission to create standards to meet the diverse technical and developmental needs of the industry.

JEDEC’s collaborative efforts ensure product interoperability, benefiting the industry and ultimately consumers by decreasing time-to-market and reducing product development costs.

JEDEC publications and standards are accepted throughout the world, and are free and open to all.

JEDEC is accredited by ANSI and maintains liaisons with numerous standards bodies throughout the world.

Locations: Global - Global
 
2020-07-01
Location: Newsletter
Description:

JEDEC publishes update to JESD22-A113I test method

JESD22-A113I, Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing, is now available for download from the JEDEC website. This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation.

 

2020-06-26
Location: Newsletter
2020-06-25
Location: Newsletter
Description:

JEDEC publishes several new and updated standards:

  • JESD79-4C: DDR4 SDRAM Standard
  • JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
  • JESD246A: Customer Notification Process for Disasters
  • JESD22-A105D: Power and Temperature Cycling
  • JESD22-B114B: Mark Legibility
  • JEP180: Guideline for Switching Reliability Evaluation
  • Procedures for Gallium Nitride Power Conversion Devices
  • Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products

Visit the JEDEC website for more information and download.

2020-06-24
Location: Newsletter
Description:

Today's Tech Buzz

Analysis: China works on catching up in chip tech

China is pressing ahead with its national program to boost the domestic semiconductor industry with the development of its own extreme ultraviolet lithography system, the beginning of memory chip production and a foundry capable of fabricating microchips with a 14-nanometer FinFET process, Mark LaPedus writes. VLSI Research President Risto Puhakka says, "China is far from being self-sufficient from any reasonable aspect."

Full Story: Semiconductor Engineering (6/22) 

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ICs, Memory & More

DRAM prices start to slide, which could weigh on Samsung

DRAMeXchange reports the spot pricing for 8-gigabit DDR4 DRAM was $2.85 on Friday, a decline of 21.6% from $3.637 on April 3, a situation that could cause concern for Samsung Electronics, the world's largest supplier of DRAMs. Meanwhile, the Korean company denied a media report that it plans to relocate its display manufacturing business in China to Ho Chi Minh City in Vietnam.

Full Story: Pulse by Maeil Business Newspaper (South Korea) (6/22),  The Korea Herald (Seoul) (6/19),  Reuters (6/19) 

 Toshiba will reduce Kioxia stake, giving cash to investors

Reuters (6/22) 

Report: TSMC will keep growing, despite Huawei sales ban

BusinessKorea magazine online (6/22) 

  ZTE reiterates it designs chips, but doesn't fabricate them

South China Morning Post (Hong Kong) (6/22) 

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Going Green

Nordic debuts chip for low-cost, two-layer PCBs

Nordic Semiconductor brought out the nRF52805 Bluetooth 5.2 system-on-a-chip device, which comes in a wafer-level chip-scale package. The low-power compact component is meant for two-layer printed circuit boards.

Full Story: Electronics Weekly (UK) (6/22) 

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Semiconductors in Action

Nvidia's A100 GPU will go into 50 server models

The A100 graphics processing unit for applications in data center is being designed into servers from Cisco Systems, Dell Technologies and dozens of other vendors. The GPU's popularity seems to stem from the accompanying A100 PCIe 4.0 card, designed for use in existing server motherboards.

Full Story: CRN (US) (6/22),  VentureBeat (6/22) 

Honeywell touts its quantum computer as faster than IBM's

Honeywell claimed its newest quantum computer surpasses the performance of IBM's supercomputer, which makes use of quantum computing technology. "What makes our quantum computers so powerful is having the highest quality qubits, with the lowest error rates," Tony Uttley, Honeywell Quantum Solutions president, said in a statement.

Full Story: TechRepublic (6/19)

Testing & Standards

UVVM tech promises to provide faster FPGA verification

The open-source Universal VHDL Verification Methodology is being touted as the fastest method for the verification of field-programmable gate array designs, this article notes. UVVM was launched in 2015 and now is used by around 20% of VHDL FPGA designers.

Full Story: New Electronics (6/22) 

JEDEC News

New guideline from JEDEC's JC-70 committee for Wide Bandgap Power Electronic Conversion Semiconductors

JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.

 

2020-06-24
Location: Newsletter
Description:

Today's Tech Buzz

Siemens will buy UltraSoC, adding SoC design analytics

Siemens agreed to acquire UltraSoC, a UK-based provider of analytics and instrumentation for system-on-a-chip device designs, for an undisclosed sum. UltraSoC CEO Rupert Baines said, "We were actually raising a B round, and when we started talking to Siemens, they saw what a strategic fit we were."

Full Story: New Electronics (6/24),  EE Times (6/23) 

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ICs, Memory & More

Omdia: Chip vendors eke out 2.1% growth in Q1 revenue

The 10 largest suppliers of semiconductors collectively posted first-quarter revenue of $63.6 billion, a 2.1% increase from the fourth quarter of 2019. "Many of the leading semiconductor suppliers benefitted from strong demand for client PCs, enterprise PCs and servers in the first quarter," Omdia's Ron Ellwanger said.

Full Story: DigiTimes (6/24) 

  Study: Chip industry needs to spread out its wafer fabs

Electronics360 (6/23) 

  TSMC wants chemical supplier TSCC to set up in the US

The Taipei Times (Taiwan) (6/24) 

  National Instruments rebrands as NI, purchases OptimalPlus

EE Times (6/24) 

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Going Green

ON Semiconductor debuts BLE chip for mesh networking

ON Semiconductor brought out a Bluetooth Low Energy device in an ultra-low-power RSL10 System-in-Package. The product is aimed at mesh networking for applications such as asset tracking and monitoring, building automation, the industrial internet of things, remote environment monitoring and smart homes.

Full Story: New Electronics (6/24)     

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Semiconductors in Action

Mercedes-Benz teams with Nvidia for automated driving

Mercedes-Benz and Nvidia will work together on developing a next-generation in-vehicle computing system for automated driving. The software-defined computing architecture will be available in 2024 models of the luxury automobile line.

Full Story: DigiTimes (6/24),  Engadget (6/23) 

Toshiba unveils 8 n-channel power MOSFETs

Toshiba is extending its DTMOSVI product line, adding eight super junction n-channel power metal-oxide-semiconductor field-effect transistors as part of its . The MOSFETs are rated for 650 volts and can be used in switched-mode power supplies for back-up power sources, data center infrastructure and power conditioners of photovoltaic generators.

Full Story: Electronics Weekly (UK) (6/24) 

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Testing & Standards

Analysis: FPGAs are well-suited for machine learning

Field-programmable gate arrays are proving to be useful for machine learning applications, this analysis notes. Shakeel Peera of Microchip Technology says, "FPGAs are specifically better at doing high-performance, low-power applications due to parallelism."

Full Story: Semiconductor Engineering (6/24) 

JEDEC News

JEDEC Updates Universal Flash Storage Standard

JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.

2020-06-23
Location: Newsletter
Description:

Today's Tech Buzz

Qualcomm's Amon touts 5G tech's potential

Cristiano Amon, president of Qualcomm, talks about what 5G cellular communications technology will mean for a variety of applications in this interview. "It allows everything to be connected -- phones, PCs, and lots of machines," he says.

Full Story: Forbes (6/22) 

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ICs, Memory & More

China's chip industry looks to 5G, EV, AIoT uses

Colley Hwang, president of DigiTimes, says China's domestic semiconductor industry will benefit from the implementation of 5G, artificial intelligence/internet of things and electric vehicles. China will play a critical role in the EV market, since six of the 10 leading suppliers of EV batteries are based in China, he notes.

Full Story: DigiTimes (6/23) 

  Intel sees chips with nanowires and nanoribbons by 2025

AnandTech (6/22) 

  GF plans Fab 8 expansion with property purchase option

Electronics Weekly (UK) (6/23) 

  4 firms join Silicon Catalyst incubator program

New Electronics (6/23) 

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Going Green

Maxim debuts Arm Cortex-M4F MCU for a variety of uses

Maxim Integrated brought out a low-power microcontroller based on the Arm Cortex-M4F core design. The chip is meant for applications in health care, industrial systems and the internet of things.

Full Story: New Electronics (6/23) 

Semiconductors in Action

Japan has the fastest supercomputer in the world

The biannual Top500 survey of the world's supercomputers reveals the fastest system now is Fugaku in Kobe, Japan, built by Fujitsu and Riken. The supercomputing system is built around Fujitsu's 48-core A64FX system-on-a-chip device, designed with Arm cores.

Full Story: The Verge (6/23) 

Leti's CoolCube process can withstand 500 degrees C

CEA-Leti reports development of the CoolCube process, fully-depleted silicon-on-insulator complementary metal-oxide-semiconductor technology that can produce chips capable of withstanding 500 degrees C during microchip manufacturing. The process could be used in making p-type MOS logic devices, according to the research organization, which collaborated with Samsung Electronics.

Full Story: Electronics Weekly (UK) (6/22) 

Testing & Standards

Analysis: Will PAM-8 follow PAM-4 in physical signaling?

PAM-4 is a key standard in high-speed physical signaling today, yet there is conjecture whether there will be a movement toward a PAM-8 standard, Bryon Moyer writes. Saman Sadr of Rambus says, "PAM-8 is not right now being that actively considered," noting that "the amplitude that we can reliably transmit is about 1V peak-to-peak."

Full Story: Semiconductor Engineering (6/23) 

JEDEC News

JEDEC welcomes new member companies to the Association

JEDEC is the global leader in developing standards for the microelectronics industry, bringing together thousands of member company volunteers over 100 technical committees and task groups to meet the needs of every segment of the industry. JEDEC is pleased to extend a warm welcome to new member companies 3D Plus, Cyntec Co., ETRI, Global Mixed-mode Technology Inc., Solid State Storage Technology Corporation and Tachyum, Inc. Interested in JEDEC membership for your company? Find out more and join today.

2020-06-19
Location: Newsletter
Description:

Today's Tech Buzz

GF, SkyWater cut a deal to make US defense chips

GlobalFoundries and SkyWater Technology agreed to act as foundries supplying critical components to the US military and aerospace industry. Senator Patrick Leahy, D-Vt., said, "This partnership helps strengthen a secure supply chain for our nation's most sensitive technology."

Full Story: New Electronics (6/19),  Reuters (6/18) 

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ICs, Memory & More

Phison will buy a stake in Sony storage unit

Phison Electronics agreed to acquire a 49% equity stake in Nextorage, a Sony Storage Media Solutions subsidiary. Financial terms weren't revealed.

Full Story: DigiTimes (6/19) 

SEMI: May's fab gear billings hit $2.35B, up 13.1% on year

DigiTimes (6/19) 

  Cambridge spinout to lead EU power module consortium

Electronics Weekly (UK) (6/18)

  Sources: GPTC wins orders for TSMC chip packaging plant

DigiTimes (6/19) 

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Going Green

Team crafts smart textile with graphene

Researchers at the UK's University of Manchester report their development of a graphene-based smart textile that could be woven into clothing. "The next step for this area of research is to address the need for dynamic thermal management of Earth-orbiting satellites," says Professor Coskun Kocabas, the research team leader.

Full Story: New Atlas (6/19)

Semiconductors in Action

Intel debuts a variety of products for AI applications

Intel brought out the third-generation "Copper Lake" Xeon Scalable processors, the Stratix 10-NX field-programmable gate array with a dedicated artificial intelligence engine, Optane memory devices and NAND flash-based solid-state drives. "We believe most of our customers do begin their journey on AI on Xeon," Intel's Lisa Spelman told reporters.

Full Story: EE Times (6/19),  ZDNet (6/18) 

Samsung offers chip design platform for fabless firms

The Samsung Advanced Foundry Ecosystem Cloud Design Platform was introduced by Samsung Electronics, providing a way for Korean fabless semiconductor companies to develop their own chips. The platform was created in collaboration with Rescale, a provider of high-performance cloud computing applications.

Full Story: Pulse by Maeil Business Newspaper (South Korea) (6/19) 

Testing & Standards

Compute-in-memory accelerators present design issues

Using a compute-in-memory accelerator is not an easy replacement for conventional logic, Katherine Derbyshire writes. "Reduced precision is often suggested as a way to improve the computational efficiency of both conventional and CIM systems," she concludes.

Full Story: Semiconductor Engineering (6/18) 

JEDEC News

JEDEC publishes several new and updated standards:

  • JESD79-4C: DDR4 SDRAM Standard
  • JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
  • JESD246A: Customer Notification Process for Disasters
  • JESD22-A105D: Power and Temperature Cycling
  • JESD22-B114B: Mark Legibility
  • JEP180: Guideline for Switching Reliability Evaluation
  • Procedures for Gallium Nitride Power Conversion Devices
  • Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products

Visit the JEDEC website for more information and download.

2020-06-18
Location: Newsletter
Description:

SK Materials becomes a Korean source for chipmaking gas, resist

SK Materials began volume production of high-purity hydrogen fluoride, a gas used in the etching process of semiconductor manufacturing. The Korean company is also investing in a plant to produce photoresist, lessening the dependence of Korean chipmakers on Japanese suppliers of resist.

Full Story: BusinessKorea magazine online

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ICs, Memory & More

Commerce Dept. clears path to developing 5G standards

Commerce Secretary Wilbur Ross defended the government's move to allow American companies to work with Huawei Technologies on developing international standards for 5G cellular communications and other areas. At the same time, he said the US government still suspects Huawei of carrying out industrial espionage and other activities that threaten national security.

Full Story: Reuters

IC Insights: Auto chips will see CAGR of 9.7% into 2024

  Electronics Weekly (UK)

Xiaomi aims at auto ICs with BYD Semiconductor funding

DigiTimes

Intel names former HP Inc. CEO Weisler to board

CRN (US)

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Going Green

Team dopes graphene with sodium for battery uses

Researchers at EPFL used sodium dopants in layers of graphene, providing an alternative material to lithium in battery technology. The resulting graphene matrix is said to provide highly efficient storage of energy.

Full Story: Tech Explorist

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Semiconductors in Action

Qualcomm debuts platform for 5G, AI robotics

Qualcomm Technologies brought out the Qualcomm Robotics RB5 platform, a single-board computer based on the company's Snapdragon 845 system-on-a-chip device design. The RB5 platform replaces the RB3, adding artificial intelligence capabilities to the product, with a development kit now available from Thundercomm.

Full Story: EE Times (6/17),  AnandTech (6/17) 

Rambus unveils IP for high-speed interfaces

Rambus introduced the 112G XSR/USR PHY intellectual property for designing high-speed interface chips. Taiwan Semiconductor Manufacturing Co. can fabricate such chips with its 7-nanometer process.

Full Story: New Electronics (6/18) 

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Testing & Standards

GaN and SiC chips look to boost their reliability

Developers of gallium nitride and silicon carbide power devices seek to improve the reliability of those chips, Mark LaPedus writes. David Haynes of Lam Research says, "The smaller form factor and performance of SiC devices is attractive for electric vehicle and hybrid electric vehicle power train applications."

Full Story: Semiconductor Engineering

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JEDEC News

JEDEC Updates Universal Flash Storage Standard

JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.

 

2020-06-16
Location: Newsletter
Description:

WT chairman: No boost for consumer chips in 2nd half | Lite-On Tech ramps up production outside of China | SK acquires 1.47% stake in BYD's chip unit for $21M

June 16, 2020

News for and about the microelectronics industry

Today's Tech Buzz

WT chairman: No boost for consumer chips in 2nd half

Eric Cheng, chairman of WT Microelectronics, says in this interview, "Compared with the past seasonal patterns, there may be no peak season for consumer-use chip products in second-half 2020, as strong demand for commercial notebooks in the first half of the year will undermine seasonal demand in the second half, with order visibility for the fourth quarter still relatively opaque." He does expect demand will hold strong for networking chips.

Full Story: DigiTimes (6/16) 

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ICs, Memory & More

Lite-On Tech ramps up production outside of China

Lite-On Technology, a provider of electronics manufacturing services, is allocating more production capacity to plants in Brazil, India, Mexico, Taiwan, Thailand and Vietnam, says CEO Warren Chen. By the end of this year, the company will have 15% to 20% of its production capacity in countries other than China, he notes.

Full Story: DigiTimes (6/16) 

§ SK acquires 1.47% stake in BYD's chip unit for $21M

Yonhap News Agency (South Korea) (free content) (6/16) 

§ Feds allow US firms to work with Huawei on 5G standards

Reuters (6/15) 

§ Samsung chief meets with CEO of semiconductor and other units

Pulse by Maeil Business Newspaper (South Korea) (6/16)

Going Green

Moortec debuts a distributed thermal sensor

Moortec Semiconductor brought out an in-chip distributed thermal sensor design, meant to be fabricated with Taiwan Semiconductor Manufacturing Co.'s 5-nanometer process, to monitor thermal activity on microchips, especially those with multiple CPU cores. Moortec CEO Stephen Crosher says, "We've seen a clear need for tighter thermal control of semiconductor devices."

Full Story: EE Times (6/15) 

Semiconductors in Action

EDA firms, Microsoft, TSMC take to the cloud for timing signoff

Synopsys worked with Taiwan Semiconductor Manufacturing Co. to optimize the PrimeTime static timing analysis and StarRC parasitic extraction tools running on the Microsoft Azure cloud-based platform. Cadence Design Systems similarly collaborated with TSMC to reduce semiconductor design signoff schedules through the cloud service.

Full Story: New Electronics (6/16),  Electronics Weekly (UK) (6/16) 

Microchip unveils Adaptec SmartRAID 3100E RAID adapters

Microchip Technology introduced Adaptec SmartRAID 3100E RAID adapters for use in data storage, edge computing and industrial/manufacturing servers. The new products promise to reduce energy consumption by 40%, the company says.

Full Story: New Electronics (6/15) 

Testing & Standards

Experts discuss the ins and outs of design verification

Five industry experts talk about how to make design verification faster and simpler in this roundtable interview. Nasr Ullah of SiFive says, "We have to use the same tools that we've used before to be much more thorough, but we also have to figure out how we can integrate all these open-source methodologies in there."

Full Story: Semiconductor Engineering (6/16) 

JEDEC News

New guideline from JEDEC's JC-70 committee for Wide Bandgap Power Electronic Conversion Semiconductors

JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.

LEARN MORE ABOUT JEDEC:

Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us

2020-06-12
Location: Newsletter
Description:

Today's Tech Buzz

NXP chooses TSMC's 5nm process for auto SoC

NXP Semiconductors is entrusting its latest automotive system-on-a-chip device design to the 5-nanometer process provided by Taiwan Semiconductor Manufacturing Co., skipping over the foundry's 7nm process. NXP and TSMC plan to sample the SoC with key automotive customers during the fall of next year.

Full Story: EE Times (6/12) 

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ICs, Memory & More

A look at the wide-bandgap semiconductor market

Gallium nitride and silicon carbide, wide-bandgap semiconductor materials, are gaining in adoption while plain silicon still dominates microchip manufacturing, this analysis notes. Yole Developpement forecasts SiC devices will represent more than 10% of market revenue by 2025, and GaN devices will provide more than 2% of the market by 2025.

Full Story: EE Times (6/12) 

§  IC designer Jim Keller departs Intel for "personal reasons"

The Verge (6/12) 

§  Synopsys buys Qualtera, adding big data analytics to design

Electronics Weekly (UK) (6/11) 

§  Mitsubishi Electric gains PMIC capacity through Sharp deal

Reuters (6/11) 

Going Green

Wearables could get a boost from supercapacitor design

An international research team came up with an environmentally friendly, high-performance, low-cost and stretchable supercapacitor that could serve as the power source for wearable gadgets. "We fabricated a prototype with unchanged performance under the 50% strain after a thousand stretching cycles," Skoltech professor Albert Nasibulin said.

Full Story: New Electronics (6/12) 

Semiconductors in Action

COVID-19 testing may turn to Bio-FET chips

Biosensing field-effect-transistor devices could be the answer to providing wider testing for COVID-19 infections, AKHAN Semiconductor CEO Adam Khan writes. "To rapidly develop and proliferate this nanocarbon technology, and meet the global demand for faster, more affordable COVID-19 testing, partnerships must be made with labs and businesses that are already working on these biosensor applications for diagnostic systems targeting of SARS-CoV2," he concludes.

Full Story: Electronic Design (6/11)  

Winbond debuts its HyperRAM WLCSP package

Winbond Electronics brought out its HyperRAM products contained in wafer-level chip-scale package. The packaging technology is suitable for embedded electronics.

Full Story: New Electronics (6/12) 

Testing & Standards

Analysis: 5nm chips are showing their age

Advanced chip designs fabricated with a 5-nanometer process are presenting new challenges in terms of device aging, Brian Bailey writes. "Semiconductor chips that operate in extreme conditions, such as automotive (150° C) or high elevation (data servers in Mexico City) have the highest risk of reliability and aging-related constraints," says Milind Weling of Intermolecular.

Full Story: Semiconductor Engineering (6/11)

JEDEC News

JEDEC Updates Universal Flash Storage Standard

JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.

LEARN MORE ABOUT JEDEC:

Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us

2020-06-03
Location: Newsletter
Description:

News for and about the microelectronics industry

Today's Tech Buzz

AMD CEO emphasizes security for US chip supply chains

Lisa Su, the CEO of Advanced Micro Devices, supports the Semiconductor Industry Association's push for more federal funding of American chip technology, while adding, "With that comes a need for secure supply chains." Meanwhile, Jon Peddie Research estimates AMD has shipped more than 500 million CPUs in the past seven years, an achievement only outdone by Intel.

Full Story: ZDNet (6/2),  Tom's Hardware (6/2) 

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ICs, Memory & More

Sources: TSMC adds SAMT as a materials supplier

Solar Applied Materials Technology is providing sputtering target materials to Taiwan Semiconductor Manufacturing Co. for front-end thin-film processes, industry sources say. SEMI notes that sputtering target materials represent around 3% of all materials used in semiconductor production.

Full Story: DigiTimes (6/3) 

§  SIA reports April chip sales of $34.4B, rising 6.2% on year

Electronics Weekly (UK) (6/3) 

§  Sources: USB chips are in shortage with stay-at-home economy

DigiTimes (6/3) 

§  Merck debuts unit for chemicals, materials, semiconductors

The Korea Herald (Seoul) (6/3) 

Going Green

ST has nearly eliminated PFOA from its processes

STMicroelectronics reports it has eliminated 94.4% of perfluorooctanoic acid (PFOA) and PFOA-related substances from its semiconductor manufacturing processes on a worldwide basis. The chipmaker has a goal of completely removing PFOA by 2025.

Full Story: Chemical Watch (subscription required) (6/2) 

Semiconductors in Action

Imagination intros IEEE 802.11ax/Wi-Fi 6 IP

Imagination Technologies brought out IMG iEW400, intellectual property complying with the IEEE 802.11ax/Wi-Fi 6 standard. The IP can be used for designing chips for hearables, the internet of things and wearables.

Full Story: New Electronics (6/2) 

NXP debuts a chip for contactless city services

NXP Semiconductors introduced the MIFARE DESFire EV3 chip meant for use in securely connecting with smart city services. The chip's hardware and software are certified to Common Criteria EAL 5+, the chipmaker reports.

Full Story: New Electronics (6/3) 

Testing & Standards

Verifying RISC-V chip designs gets easier

With wider adoption of the open-source RISC-V instruction-set architecture, verifying processor designs are becoming less onerous, this analysis notes. Roddy Urquhart of Codasip says, "Developing and verifying RISC-V designs is not fundamentally different to other processor architectures."

Full Story: Semiconductor Engineering (6/3) 

JEDEC News

JEDEC Updates Universal Flash Storage Standard

JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.

LEARN MORE ABOUT JEDEC:

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2020-04-20
Location: Newsletter
Description:

New guideline from JEDEC's JC-70 committee for Wide Bandgap Power Electronic Conversion Semiconductors

JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.

 

2020-03-21
Location: Newsletter
Description:

JEDEC publishes several new and updated standards:

  • JESD79-4C: DDR4 SDRAM Standard
  • JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
  • JESD246A: Customer Notification Process for Disasters
  • JESD22-A105D: Power and Temperature Cycling
  • JESD22-B114B: Mark Legibility
  • JEP180: Guideline for Switching Reliability Evaluation
  • Procedures for Gallium Nitride Power Conversion Devices
  • Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
2020-03-17
Location: Newsletter
Description:

EDA, verification support crucial to HPC packaging

High-end high performance computing (HPC) chips solutions are entailing ever-rising packaging complexity along with their increasing applications to large-size datacenters and networking equipment beyond handsets, and this has made EDA (electronic design automation) tools and IC verification services growingly crucial to packaging.

The fast spread of the coronavirus pandemic is fueling needs for work-from-home, online teleconferencing and other stay-at-home economic activities, requiring HPCs to handle cloud computing and big data processing via large-size network equipment and datacenters.

Industry sources said with new large-size HPCs requiring ever-higher computing performance, advanced CoWoS packaging process, based on silicon interposer, continues to adopt larger reticles to integrate more SoCs and high bandwidth memory chips. In this regard, EDA tools for the initial simulation support and following reliability analysis and test for HPCs are important in the entire process.

Taiwan-based IC verification specialists such as Integrated Service Technology (iST) and EDA tools providers including Ansys all have roles in the advanced packaging processes. Ansys' newly released RaptorH can help engineers improve design procedures for diverse HPCs such as 5G chips, 3D ICs and RF (radio frequency) ICs for applications to smart mobile devices, antennas, data storage systems and network infrastructure, as well as even autonomous vehicles and industrial control systems, the sources said.

Reliability analysis for large-size network and datacenter HPC solutions adopting advanced packaging technology usually will take two weeks to complete, double that for handset applications and allowing analysts to charge more, the sources continued.

At the moment, foundry giant TSMC's WLSI (wafer level system integration) platform can provide the world's first-tier chipmakers, IDMs and system vendors with sound integrated HPC chips solutions. The company now uses InFo_PoP and InFO-AiP to package iPhone APs and antenna modules, and its derived technologies InFO_oS and InFO_MS will focus on processing networking and datacenter HPCs, the sources said. Dedicated backend houses such as ASE Technology can also use its 2.5D IC packaging technology such as FOCoS to serve chipmakers.

2020-03-17
Location: Newsletter
Description:

HPC chip packaging complexity calls for EDA, verification

The increasing complexity of advanced packaging for high-performance computing chips is driving demand for electronic design automation software tools and IC verification services. Those HPC chips are going into large-scale data centers and networking equipment.

Full Story: DigiTimes (3/16) 

2020-03-16
Location: Newsletter
Description:

New guideline from JEDEC's JC-70 committee for Wide Bandgap Power Electronic Conversion Semiconductors

JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.

2020-03-13
Location: Newsletter
2020-03-11
Location: Newsletter
Description:

JEDEC publishes several new and updated standards:

  • JESD79-4C: DDR4 SDRAM Standard
  • JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
  • JESD246A: Customer Notification Process for Disasters
  • JESD22-A105D: Power and Temperature Cycling
  • JESD22-B114B: Mark Legibility
  • JEP180: Guideline for Switching Reliability Evaluation
  • Procedures for Gallium Nitride Power Conversion Devices
  • Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
2020-03-06
Location: Newsletter
Description:

New guideline from JEDEC's JC-70 committee for Wide Bandgap Power Electronic Conversion Semiconductors

JEP180: Guideline for Switching Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices is available for free download from the JEDEC website. To enable the successful adoption of GaN power transistors, both reliable operation in power conversion applications and switching lifetime need to be demonstrated. Existing tests for silicon power transistors do not necessarily validate operation under actual-use conditions of power conversion equipment and may not be applicable for GaN power transistors. To address this need, JEP180 is intended for use by manufacturers of GaN power transistors and power conversion equipment.

2020-03-04
Location: Newsletter
Description:

JEDEC Updates Universal Flash Storage Standard

JEDEC has published UFS version 3.1: JESD220E. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, is also available. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. Both JESD220E and JESD220-3 are available for download from the JEDEC website.

2020-03-04
Location: Newsletter
Description:

JEDEC publishes several new and updated standards:

  • JESD79-4C: DDR4 SDRAM Standard
  • JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
  • JESD246A: Customer Notification Process for Disasters
  • JESD22-A105D: Power and Temperature Cycling
  • JESD22-B114B: Mark Legibility
  • JEP180: Guideline for Switching Reliability Evaluation
  • Procedures for Gallium Nitride Power Conversion Devices
  • Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
2020-02-21
Location: Newsletter
Description:

JEDEC publishes several new and updated standards:

  • JESD79-4C: DDR4 SDRAM Standard
  • JESD209-4C: Low Power Double Data Rate 4 (LPDDR4)
  • JESD246A: Customer Notification Process for Disasters
  • JESD22-A105D: Power and Temperature Cycling
  • JESD22-B114B: Mark Legibility
  • Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products
2019-12-13
Description:

Updates to JEP95: JEDEC Registered and Standard Outlines for Solid State and Related Products now available for free download

JEP95 is a compilation of some 3000 pages of outline drawings for microelectronic packages. An annual updating service and complete hard copies are available for purchase in addition to the downloads available on the JEDEC website. For more information and recent updates visit the JEP95 page on the JEDEC website.

 

2019-12-06
Location: Newsletter
Description:

JEDEC publishes several new and updated standards

  • JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
  • JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
  • JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
  • JESD30I: Descriptive Designation System for Electronic-Device Packages
  • JESD245C: Byte Addressable Energy Backed Interface

Read more about these standards.

Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us  

2019-12-04
Location: Newsletter
Description:

Today's Tech BuzZ-

Ministry: Japan to make more transistors than the US

Japan's Ministry of International Trade and Industry reports the country will be producing 6 million transistors a month by the end of the year, outdoing the US for monthly transistor manufacturing.

Electronics Weekly (UK) (12/3) 

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ICs, Memory & More

Intel's chip shortage drives Dell to look at AMD chips

Dell is considering the use of chips supplied by Advanced Micro Devices in light of Intel's continuing problems in making enough CPUs for market demands. "We are evaluating AMD chips," said Tom Sweet, Dell's chief financial officer, in an interview; adding that the computer manufacturer already uses AMD chips in particular instances.

Yahoo (12/3) 

Court upholds Korean fine against Qualcomm; appeal planned

Qualcomm plans to appeal a ruling by a South Korean court upholding an $873 million fine for unfair business practices in patent licensing and modem chip sales. Meanwhile, Qualcomm debuted the 3D Sonic Max ultrasonic in-display fingerprint sensor, which can read two fingerprints at the same time, and revealed some details about the forthcoming Snapdragon 865 Mobile Platform and Snapdragon 765/765G mobile platform.

Reuters (12/3),  ZDNet (12/3),  The Verge (12/3) 

2020 forecasts see single-digit growth for chip sales    Electronics Weekly (UK) (12/4) 

Going Green

Team touts organic semiconductors for next-gen electronics

Sensors, solar cells and other devices may perform better if made from organic semiconductor materials, Rutgers University researchers report. "If implemented in electrical circuits, such an enhancement - achieved by very slight bending -- would mean a major leap toward realizing next-generation, high-performance organic electronics," said Professor Vitaly Podsorov, senior author of the study.

New Electronics (12/4) 

Semiconductors in Action

UNISOC licenses Imagination's AI chip tech

UNISOC licensed the IMG Series3NX neural network accelerator intellectual property from Imagination Technologies for use in designing system-on-a-chip devices for mobile electronics, televisions and other applications. Meanwhile, Imagination brought out the IMG A-Series graphics processing unit IP, representing the 10th generation of its PowerVR GPU architecture.

New Electronics (12/4),  Electronics Weekly (UK) (12/3) 

Amazon unveils the AWS Graviton 2 processor for data centers    Reuters (12/3) 

Testing & Standards

Chipmakers consider their options in EUV lithography

Intel, Samsung Electronics and Taiwan Semiconductor Manufacturing Co. are urging ASML to speed up development of its EXE:5000 extreme ultraviolet lithography system with a high-numerical-aperture lens, which could pattern chips with 3-nanometer features. Those chipmakers are currently using the NXE:3340C system for multiple patterning with 5nm/3nm chip production.

Semiconductor Engineering (12/4) 

JEDEC News

JEDEC Announces Publication of Serial Presence Detect Support and Module Labels Specifications to Support New Hybrid Memory (NVDIMM)

JEDEC has published document release 5 of the DDR4 Serial Presence Detect (SPD) Specification. With this release of the document, the revision level of all memory types increases to UDIMM (revision 1.2), RDIMM (revision 1.3), LRDIMM (revision 1.4) and NVDIMM (revision 1.2). In addition, JEDEC has issued document release 1 of the DDR4 DIMM Labels Specification.

Learn more about JEDEC:

Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us

 

 

2019-11-26
Location: Newsletter
Description:

JEDEC News

JEDEC publishes several new and updated standards

  • JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
  • JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
  • JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
  • JESD30I: Descriptive Designation System for Electronic-Device Packages
  • JESD245C: Byte Addressable Energy Backed Interface

Read more about these standards.

Learn more about JEDEC:

Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us

Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package

Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959

MO-341A

Oct 2019

view

Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20

MO-340A

Oct 2019

view

STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm

JEP106BA

Oct 2019

view

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.

JEP162A

Sep 2019

view

Registration - Plastic Bottom Flatpack 28 Terminal Package

Item 11-11.975, STP File for MO-339A

MO-339A

Sep 2019

view

Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package

Item 11.11-973, Access STP Files for MO-338A

MO-338A

Sep 2019

view

JEDEC News

JEDEC publishes several new and updated standards

  • JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
  • JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
  • JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
  • JESD30I: Descriptive Designation System for Electronic-Device Packages
  • JESD245C: Byte Addressable Energy Backed Interface

Read more about these standards.

Learn more about JEDEC:

Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us

Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package

Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959                                                                                       MO-341A             Oct 2019        view

Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20                                                   MO-340A             Oct 2019        view

STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm                                                                                                               JEP106BA             Oct 2019        view

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.                                                                      JEP162A    Sep 2019   view

Registration - Plastic Bottom Flatpack 28 Terminal Package

Item 11-11.975, STP File for MO-339A                                                       MO-339A             Sep 2019       view

Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package

Item 11.11-973, Access STP Files for MO-338A                                          MO-338A             Sep 2019       view

 

 

2019-11-26
Location: Newsletter
Description:

JEDEC News

JEDEC publishes several new and updated standards

  • JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
  • JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
  • JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
  • JESD30I: Descriptive Designation System for Electronic-Device Packages
  • JESD245C: Byte Addressable Energy Backed Interface

Read more about these standards.

Learn more about JEDEC:

Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us

Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package

Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959

MO-341A Oct 2019  view

Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20

MO-340A Oct 2019  view

STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm

JEP106BA Oct 2019  view

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.

JEP162A Sep 2019  view

Registration - Plastic Bottom Flatpack 28 Terminal Package

Item 11-11.975, STP File for MO-339A

MO-339A Sep 2019  view

Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package

Item 11.11-973, Access STP Files for MO-338A

MO-338A Sep 2019 view

JEDEC News

JEDEC publishes several new and updated standards

  • JEP162A: System Level ESD: PART II: Implementation of Effective ESD Robust Designs
  • JESD216D.01: Serial Flash Discoverable Parameters (SFDP)
  • JESD8-33: 0.5 V Low Voltage Swing Terminated Logic (LVSTL05)
  • JESD30I: Descriptive Designation System for Electronic-Device Packages
  • JESD245C: Byte Addressable Energy Backed Interface

Read more about these standards.

Learn more about JEDEC:

Join JEDEC | Free Standards Download
Events & Meetings | News | Contact Us

Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package

Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959                                                                                          MO-341A             Oct 2019        view

Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20                                                     MO-340A             Oct 2019        view

STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm 

JEP106BA             Oct 2019                       view

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.                                                                     

 JEP162A    Sep 2019   view

Registration - Plastic Bottom Flatpack 28 Terminal Package

Item 11-11.975, STP File for MO-339A                                                         MO-339A             Sep 2019       view

Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package

Item 11.11-973, Access STP Files for MO-338A                                            MO-338A             Sep 2019       view

 

 

2019-11-22
Location: Newsletter
Description:

News for and about the microelectronics industry

Today's Tech Buzz

Senators call for stop on Huawei license approvals

Fifteen senators called on the Trump administration to suspend issuing licenses to US companies that do business with Huawei Technologies, claiming the Chinese company presents a threat to national security. In a letter to President Donald Trump, the bipartisan group says the Commerce Department licenses will enable "Huawei to continue to pose a serious threat to US telecommunications infrastructure and national security more broadly."

Reuters (11/21)

ICs, Memory & More

Micron CEO sees "healthy demand trends" in DRAM market

Micron Technology CEO Sanjay Mehrotra credits artificial intelligence, the internet of things and other applications for increasing use of DRAMs. "When I look beyond the calendar first quarter of 2020, I see healthy demand trends for DRAM in all end markets," he said in an interview, adding, "There is still excessive inventory in the DRAM industry and producers, but the inventory is coming down fast."

The Taipei Times (Taiwan) (11/22)

President of S. Korea lauds new silicon wafer plant

President Moon Jae-in attended the opening of MEMC Korea's silicon wafer plant in Cheonan, Korea, saying it would reduce the country's reliance on importing silicon wafers for its semiconductor industry. MEMC Korea is a subsidiary of Taiwan-based GlobalWafers.

The Korea Herald (Seoul)/Yonhap News Agency (11/22)

Going Green

$10M more invested in IoT energy harvesting startup

Disruptive Technology Ventures invested another $10 million in Nowi, a designer of energy harvesting chips, expanding the startup's Series A funding by DTV and the Dutch government. "This new $10 million Series A round of funding enables Nowi to further grow the team and complete the transition from start-up to a mature organization, while still retaining a majority position in the company," said Nowi CEO Simon van der Jagt.

Electronics Weekly (UK) (11/21)

Semiconductors in Action

Supermicro, Intel team for distributed-training AI systems

Super Micro Computer is working with Intel on artificial intelligence systems using the chipmaker's Nervana Neural Network Processor for Training. The processor is a purpose-built, application-specific integrated circuit supporting deep learning training models.

New Electronics (11/21)

Testing & Standards

Panel-level fan-out packaging tech gains in adoption

More companies are turning to panel-level fan-out packaging technology, a successor to wafer-level fan-out packaging, as a method to reduce the costs of advanced packaging, this analysis notes. SEMI is considering a standard on panel sizes, narrowing the specifications to 510mm x 515mm and 600mm x 600mm.

Semiconductor Engineering (11/21)

JEDEC News

JEDEC Announces Publication of Serial Presence Detect Support and Module Labels Specifications to Support New Hybrid Memory (NVDIMM)

JEDEC has published document release 5 of the DDR4 Serial Presence Detect (SPD) Specification. With this release of the document, the revision level of all memory types increases to UDIMM (revision 1.2), RDIMM (revision 1.3), LRDIMM (revision 1.4) and NVDIMM (revision 1.2). In addition, JEDEC has issued document release 1 of the DDR4 DIMM Labels Specification.

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2019-11-21
Location: Newsletter
Description:

News for and about the microelectronics industry

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Today's Tech Buzz

Commerce Dept. to grant, deny licenses for Huawei sales

The US Department of Commerce said Wednesday that it would grant "several licenses" to American companies, allowing them to continue their sales to Huawei Technologies, while adding it would deny some license applications. Broadcom, Google, Intel, Microsoft and Qualcomm all declined to comment on the license issue.

CNN (11/21)

A programmable memristor computer on CMOS
As machine learning and AI demands grow, memory bottlenecks have bogged down innovation. To get around limitations of on-chip memory and the cloud, University of Michigan has made the first memristor-based programmable computer, reports IEEE.

ICs, Memory & More

Intel: PC chip supplies still short, turns to foundries

Intel said its chips for PCs remain in short supply, adding it would provide more orders to foundries for producing those scarce devices. "I'd like to acknowledge and sincerely apologize for the impact recent PC CPU shipment delays are having on your business and to thank you for your continued partnership," Intel's Michelle Johnston Holthaus wrote in a letter to customers and partners.

Reuters (11/20), The Business Journals (tiered subscription model)/Portland, Ore. (11/20)

FOPLP is an alternative to IC scaling, PTI chairman says

Fan-out panel-level packaging technology offers a suitable alternative to continued scaling for chip designs, says DK Tsai, chairman of Powertech Technology. FOPLP can be used to produce high-performance computing chipsets without resorting to advanced process nodes, such as 7-nanometer and 5nm, he asserts.

DigiTimes (11/21)

Going Green

TT Electronics offers lead-free GBCN for RoHS compliance

TT Electronics expanded its line of GBCN thick-film gate arrays that do not contain lead or lead compounds. These gate arrays are suitable to meet the European Union's Restriction of Hazardous Substances directive, the distributor says.

Electronics Weekly (UK) (11/21)

Semiconductors in Action

Renesas aims at industrial automation with ASSP

Renesas Electronics brought out the ASI4U application-specific standard product chip, complying with the Actuator Sensor Interface version specification version 5 standard. The ASSP is meant for use in industrial networking systems.

New Electronics (11/20)

Testing & Standards

DRAM tech approaches its physical limits

DRAM technology is getting closer to its physical limits, making the memory chips harder to produce at 10 nanometers and lower process nodes, Mark LaPedus writes. Gill Lee of Applied Materials wrote in a blog post, "With DRAM, geometric lateral scaling continues, but it is slowing and materials innovation will be needed for further scaling as with 3D NAND."

Semiconductor Engineering (11/21)

JEDEC News

DDR4 design specifications published

Recent updates to JESD21-C: JEDEC Configurations for Solid State Memories include DDR4 Unbuffered DIMM and SODIMM specifications. For more information visit the JESD21-C page on the JEDEC website.

Learn more about JEDEC:

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2019-09-26
Location: Santa Clara, Ca and Taiwan
Description:

October 7-10, 2019 - Santa Clara, CA

October 14-17, 2019 - Hsinchu, Taiwan

LAST CHANCE - Advance  Registration Ends 9/27

Join us for exclusive, pre-publication insight into the JEDEC DDR5, LPDDR5 and NVDIMM-P standards. Get ahead of the competition with in-depth technical reviews taught by industry experts involved in the development of these standards.

JEDEC DDR5 memory will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency. These enhancements, combined with a more user-friendly interface for server and client platforms, will enable high performance and improved power management in a wide variety of applications.

The JEDEC NVDIMM-P standard will enable the industry to create Persistent Memory solutions optimized for cost, power utilization and performance. Adding to the existing NVDIMM-N JEDEC standards, NVDIMM-P modules are designed to maximize the benefits of new Persistent Memory media including reduced software overhead, capacity expansion and lowest latency in computing systems.

JEDEC LPDDR5 is designed to significantly boost memory speed and efficiency for a variety of applications including mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. In addition, LPDDR5 offers new features designed for mission critical applications such as automotive.

On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.

LAST CHANCE to save: advance registration for Santa Clara ends 9/27! Higher onsite registration rates will go into effect thereafter. Registration is a la carte - pick and choose the topics that interest you.

Registration - CA
Registration - Taiwan

Event Dates & Locations

  • October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
  • October 7, 2019 - Memory Tutorial Santa Clara, CA
  • October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
  • October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
  • October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
  • October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
  • October 15-16 - DDR5 Workshop Hsinchu, Taiwan

October 17 - NVDIMM-P Workshop Hsinchu, Taiwan

 

2019-09-11
Location: California
Description:

October 7-10, 2019 - Santa Clara, CA

October 14-17, 2019 - Hsinchu, Taiwan

Register now - registration closes soon!

Join us for exclusive, pre-publication insight into the JEDEC DDR5, LPDDR5 and NVDIMM-P standards. Get ahead of your competition with in-depth technical reviews taught by industry experts involved in the development of these standards.

On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.

Act now - space is limited and registration closes 9/27 or when available space is filled!

Registration - CA
Registration - Taiwan

Event Dates & Locations

  • October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
  • October 7, 2019 - Memory Tutorial Santa Clara, CA
  • October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
  • October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
  • October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
  • October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
  • October 15-16 - DDR5 Workshop Hsinchu, Taiwan
  • October 17 - NVDIMM-P Workshop Hsinchu, Taiwan

Santa Clara Event Sponsor

Industry Sponsor: DDR5 Workshop Santa Clara

Tto download JEDEC standards at www.jedec.org.

Our mailing address is:

JEDEC

3103 North 10th Street

Suite 240S

Arlington, Va 22201

2019-09-04
Location: Santa Clara, Ca and Taiwan
Description:

JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Memory Tutorial: A DDR5 Workshop Companion

October 7-10, 2019 - Santa Clara, CA

Register now - online registration ends soon!

The JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops in Santa Clara, CA and Hsinchu, Taiwan will offer participants an unparalleled opportunity to receive an in-depth technical review of these standards. On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.

Registration is now open for events in California! Act now - space is limited!

Event Dates & Locations

  • October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
  • October 7, 2019 - Memory Tutorial Santa Clara, CA
  • October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
  • October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
  • October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
  • October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
  • October 15-16 - DDR5 Workshop Hsinchu, Taiwan
  • October 17 - NVDIMM-P Workshop Hsinchu, Taiwan

Interested in the events in Taiwan? Register here.

Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.

 

2019-08-20
Location: Newsletter
Description:

JEDEC Workshops: DDR5, LPDDR5, NVDIMM-P

Memory Tutorial: A DDR5 Workshop Companion

October 7-10, 2019 - Santa Clara, CA

October 14-17, 2019 - Hsinchu, Taiwan

Register now - space is limited

Join us for an in-depth technical review of these standards with industry experts directly involved in their development.

LPDDR5 is designed to significantly boost memory speed and efficiency for a variety of applications including mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. In addition, LPDDR5 offers new features designed for mission critical applications such as automotive.

DDR5 will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency.

NVDIMM-P: As demand for DRAM capacity and bandwidth continues to grow within systems, Hybrid DIMM technologies such as JEDEC NVDIMM-P will enable new memory solutions optimized for cost, power usage and performance.

A companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.

Registration is now open for events in California! Act now - space is limited!

Event Dates & Locations

  • October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
  • October 7, 2019 - Memory Tutorial Santa Clara, CA
  • October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
  • October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
  • October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
  • October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
  • October 15-16 - DDR5 Workshop Hsinchu, Taiwan
  • October 17 - NVDIMM-P Workshop Hsinchu, Taiwan

Interested in the events in Taiwan? Register here.

Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.

Copyright © 2019 JEDEC, All rights reserved.
to download JEDEC standards at www.jedec.org.

Our mailing address is:

JEDEC

3103 North 10th Street

Suite 240S

Arlington, Va 22201

 

2019-08-07
Location: Santa Clara, Ca and Taiwan
Description:

Join us for an in-depth technical review of these standards with industry experts directly involved in their development.

LPDDR5 is designed to significantly boost memory speed and efficiency for a variety of applications including mobile computing devices such as smartphones, tablets, and ultra-thin notebooks. In addition, LPDDR5 offers new features designed for mission critical applications such as automotive.

DDR5 will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency.

NVDIMM-P: As demand for DRAM capacity and bandwidth continues to grow within systems, Hybrid DIMM technologies such as JEDEC NVDIMM-P will enable new memory solutions optimized for cost, power usage and performance.

A companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.

Registration is now open for events in California! Act now - space is limited!

        Event Dates & Locations

  • October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
  • October 7, 2019 - Memory Tutorial Santa Clara, CA
  • October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
  • October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
  • October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
  • October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
  • October 15-16 - DDR5 Workshop Hsinchu, Taiwan
  • October 17 - NVDIMM-P Workshop Hsinchu, Taiwan

Interested in the events in Taiwan? Register here

  Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.

JEDEC Workshops: DDR5, LPDDR5, NVDIMM-P

Memory Tutorial: A DDR5 Workshop Companion
October 7-10, 2019 - Santa Clara, CA

October 14-17, 2019 - Hsinchu, Taiwan

Register now - space is limited

 

2019-07-29
Location: Santa Clara, Ca and Taiwan
Description:

JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Memory Tutorial: A DDR5 Workshop Companion

October 7-10, 2019 - Santa Clara, CA

Register now - space is limited

The JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops in Santa Clara, CA and Hsinchu, Taiwan will offer participants an unparalleled opportunity to receive an in-depth technical review of these standards. On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.

Registration is now open for events in California!  Act now - space is limited! 

Event Dates & Locations

  • October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
  • October 7, 2019 - Memory Tutorial Santa Clara, CA
  • October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
  • October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
  • October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
  • October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
  • October 15-16 - DDR5 Workshop Hsinchu, Taiwan
  • October 17 - NVDIMM-P Workshop Hsinchu, Taiwan

Interested in the events in Taiwan? Pre-register here.

Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.

2019-07-15
Location: Santa Clara, Ca and Taiwan
Description:

JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Memory Tutorial: A DDR5 Workshop Companion

October 7-10, 2019 - Santa Clara, CA

Register now - space is limited

The JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops in Santa Clara, CA and Hsinchu, Taiwan will offer participants an unparalleled opportunity to receive an in-depth technical review of these standards. On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.
Pre-registration is now open for events in California! Act now for discounted pricing on two bundle options. A la carte event registration will be available starting July 17, space permitting.

Event Dates & Locations

  • October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
  • October 7, 2019 - Memory Tutorial Santa Clara, CA
  • October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
  • October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
  • October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
  • October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
  • October 15-16 - DDR5 Workshop Hsinchu, Taiwan
  • October 17 - NVDIMM-P Workshop Hsinchu, Taiwan

Interested in the events in Taiwan? Pre-register here.

Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.

JEDEC

3103 North 10th Street

Suite 240S

Arlington, Va 22201

Archived Events: (Click to expand/collapse)
2019-06-27
Location: Santa Clara, Ca and Taiwan
Description:

-JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops
Memory Tutorial: A DDR5 Workshop Companion

October 7-10, 2019 - Santa Clara, CA

Register now - space is limited

The JEDEC DDR5, LPDDR5 and NVDIMM-P Workshops in Santa Clara, CA and Hsinchu, Taiwan will offer participants an unparalleled opportunity to receive an in-depth technical review of these standards. On the day before the DDR5 Workshop, a companion Memory Tutorial class will be offered. Covering every DRAM generation, the Memory Tutorial is an essential prerequisite for prospective DDR5 Workshop attendees who do not have significant experience with DDR4 memory technology.

Pre-registration is now open for events in California! Act now for discounted pricing on two bundle options. A la carte event registration will be available starting July 17, space permitting. Registration for the events in Taiwan will open soon.

Option #1: Memory Tutorial, DDR5 & NVDIMM-P Workshops
JEDEC Members: $1,050
Non-members: $1,275

Option #2: LPDDR5, DDR5 & NVDIMM-P Workshops
JEDEC Members: $1,275
Non-members: $1,500

Event Dates & Locations

  • October 7, 2019 - LPDDR5 Workshop Santa Clara, CA
  • October 7, 2019 - Memory Tutorial Santa Clara, CA
  • October 8-9, 2019 - DDR5 Workshop Santa Clara, CA
  • October 10, 2019 - NVDIMM-P Workshop Santa Clara, CA
  • October 14, 2019 - LPDDR5 Workshop Hsinchu, Taiwan
  • October 14, 2019 - Memory Tutorial Hsinchu, Taiwan
  • October 15-16 - DDR5 Workshop Hsinchu, Taiwan
  • October 17 - NVDIMM-P Workshop Hsinchu, Taiwan

-Sponsorships
A limited number of sponsorships are available for the California events on a first-come, first-served basis. More information here.

www.jedec.org

 

 

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