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CHiL Semiconductor

Shaping Efficiency Using CHiL Semiconductor Digital Algorithms

The onslaught of efficiency requirements emerging throughout the computing industry for multiphase DC-DC voltage regulators has caused a major shift in VR solutions.   While industry specifications such as Climate Savers or Energy Star for computing do not specify exact DC-DC efficiency requirements, they make it clear that efficiency from 20% to 100% load needs to constantly improve.  Major OEM customers, especially in the server industry, are demanding even higher efficiency than the industry forums indicate.   CHiL Semiconductor Corporation has implemented several digital algorithms in their digital power management IC families, to shape the efficiency across the entire load of the CPU as well as the memory.

Efficiency Evolution and Shaping

The efficiency of VR solutions, whether for CPU or Memory on Servers, or for Graphics controllers on graphics boards or in High Performance Computing applications, has evolved over time as a function of cost and size.  Total Cost of Ownership (TCO) has entered into the equation as well as the concern for Greener solutions, driving the need for higher efficiency.   Figure 1, indicative of multiphase systems converting 12V to 1.2V, highlights the evolution of efficiency in servers over the last several years.  

Initially, efficiency and TCO were not a concern, and efficiency typically peaked near the 88% range.  At lower currents, in idle states, the efficiency dropped off due to the switching losses of multiple phases.  The industry next introduced the power savings indicator, (PSI) that allowed VR solutions to turn off all but one phase at lower load currents, raising the efficiency in idle states.  The efficiency over various operating modes, especially in Servers where 20-100% operation is the most important, was still quite low.   Solutions that strived to achieve higher efficiency would use discrete MOSFETs with lower RDSon in the solution, driving the higher load efficiency to higher points, costing efficiency at lower loads due to increased drive losses.  Integrated solutions, whether monolithic or multi-chip, reduced parasitic losses and increased efficiencies at the low range.

CHiL’s digital algorithms combine to create a shaped efficiency curve, that results in the high efficiency across the entire load line.   It is accomplished through two primary methodologies – Dynamic Phase Control as well as Variable Gate Drive.  

Dynamic Phase Control

Dynamic Phase Control (DPC) is the fast, controlled management of phases in a multiphase VR solution, combining the shedding of phases as a function of average current, and extremely fast and controlled addition of phases as a function of peak or transient currents as well as average current.

Phase shedding, as it has been coined, is quite easily implemented in VR solutions.   By simply measuring the average current and reducing the number of operating phases, switching losses can be mitigated.  While a simple concept, it has not been effectively implemented in Servers in the past because of the need to respond to large increases in current due to CPU, Memory or GPU transients.   Adding phases slowly is an unacceptable solution as it will (a) result in the saturation of inductors or (b) will require an excess of bulk capacitors on the output of the VR solution to hold the voltage while the phases are added.  CHiL’s non-linear approach to the addition of phases overcomes these issues.  

A six phase server VR solution utilizing DPC is shown in Figure 2, where the load current is changed at high speed from 105A to 30A and back to 105A. This example utilized no more bulk capacitors than is required for normal transient responses.  The response to a load release is a controlled dropping of phases one at a time to reach the ideal efficiency operating point at 30A which is two phases in this example.  The response to the load step increase is very fast controlled turn-on of the phases in order to ramp the current in the inductors and drive the current to the load.  A careful examination of the timing of the 4 additional phases turning on will show that they are not turned on exactly at the same time. The algorithm used manages the timing frequency and pulse width of each phase turning on to minimize overshoot but to also minimize common analog problems such as ringback, the overshoot caused by driving too much current into the output stage too quickly.

 

Variable Gate Drive

A second mechanism to achieve higher efficiency across the load is to manage the gate drive to the MOSFETs or powerstage device as a function of the load current, called Variable Gate Drive (VGD).  Normal server solutions usually choose a gate drive voltage that is either 12V, 5V or an intermediate voltage that is chosen to optimize the RDSon at only one operating point.   Some systems will toggle between 12V  and 5V at lower currents.  No one fixed gate drive voltage is ideal.  CHiL has implemented a programmable gate drive algorithm that allows the user to vary the gate drive voltage from any point at low currents to any other point at higher currents.   A typical example may vary the voltage from 5V to 9V.   5V operation at lower currents save significant gate drive losses while 9V operation at high loads reduce RDSon to its minimum value while not overdriving the MOSFETs, i.e., 12V operation. 

The effects of VGD in a low cost four-phase desktop design are shown in Figure 3.   Dynamic Phase Control, discontinuous mode and PSI operations are turned off to show the effects of varying the gate drive in the system.   The efficiency is improved by 10% at 10A, and by 1-3 % at higher currents.

 

Conclusion

Implementing the Dynamic Phase Control and the Variable Gate Drive algorithms as shown in this paper result in a shaped efficiency that increases efficiency across the entire load. Likewise, these algorithms are independent of any particular power devices or gate drivers, so that any VR solution can improve the efficiency above what they have, not matter what device they are using.

Provided by David Williams,
Director, Systems Engineering,
CHiL Semiconductor

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